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ST72344S2 датащи(PDF) 89 Page - STMicroelectronics |
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ST72344S2 датащи(HTML) 89 Page - STMicroelectronics |
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89 / 247 page ![]() ST72344xx, ST2345xx On-chip peripherals Doc ID 12321 Rev 6 89/247 Figure 41. Main clock controller (MCC/RTC) block diagram 11.2.5 Low-power modes 11.2.6 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction). DIV 2, 4, 8, 16 MCC/RTC INTERRUPT SMS CP1 CP0 TB1 TB0 OIE OIF CPU CLOCK MCCSR 12-BIT MCC RTC COUNTER TO CPU AND PERIPHERALS fOSC2 fCPU MCO MCO BC1 BC0 MCCBCR BEEP SELECTION BEEP SIGNAL 1 0 TO WATCHDOG TIMER DIV 64 Table 39. Mode description Mode Description Wait No effect on MCC/RTC peripheral. MCC/RTC interrupt cause the device to exit from Wait mode. Active-halt No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from Active-halt mode. Halt MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit from Halt” capability. Table 40. Interrupt event Interrupt event Event flag Enable Control bit Exit from Wait Exit from Halt Time base overflow event OIF OIE Yes No (1) 1. The MCC/RTC interrupt wakes up the MCU from Active-halt mode, not from Halt mode. |
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