ST72344S2 datasheet(163/247 Pages) STMICROELECTRONICS

163 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

163/247

Bit 4 = AF Acknowledge failure.

This bit is set by hardware when no acknowledge is returned. An interrupt is generated

if ITE=1. It is cleared by software reading SR2 register or by hardware when the

interface is disabled (PE=0).

The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at

the same time.

0: No acknowledge failure

1: Acknowledge failure

Bit 3 = STOPF Stop detection (Slave mode).

This bit is set by hardware when a Stop condition is detected on the bus after an

acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software

reading SR2 register or by hardware when the interface is disabled (PE=0).

The SCL line is not held low while STOPF=1.

0: No Stop condition detected

1: Stop condition detected

Bit 2 = ARLO Arbitration lost.

This bit is set by hardware when the interface loses the arbitration of the bus to another

master. An interrupt is generated if ITE=1. It is cleared by software reading SR2

After an ARLO event the interface switches back automatically to Slave mode

(M/SL=0).

The SCL line is not held low while ARLO=1.

0: No arbitration lost detected

1: Arbitration lost detected

Note:

In a Multimaster environment, when the interface is configured in Master Receive mode it

does not perform arbitration during the reception of the Acknowledge Bit. A mishandling of

the ARLO bit from the I2CSR2 register may occur when a second master simultaneously

requests the same data from the same slave, and the I2C master does not acknowledge the

data. The ARLO bit is then left at 0 instead of being set.

Bit 1 = BERR Bus error.

This bit is set by hardware when the interface detects a misplaced Start or Stop

condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2

The SCL line is not held low while BERR=1.

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

Note:

If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the

Master to re-synchronize communication, get the transmission acknowledged and the bus

released for further communication

Bit 0 = GCAL General Call (Slave mode).

This bit is set by hardware when a general call address is detected on the bus while

ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the

interface is disabled (PE=0).

0: No general call address detected on the bus

1: General call address detected on the bus

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