ST72344S2 datasheet(162/247 Pages) STMICROELECTRONICS

162 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

162/247

Doc ID 12321 Rev 6

Figure 69). BTF is cleared by reading SR1 register followed by writing the next byte in

DR register.

●

Following a byte reception, this bit is set after transmission of the acknowledge clock

pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte

from DR register.

The SCL line is held low while BTF=1.

0: Byte transfer not done

1: Byte transfer succeeded

Bit 2 = ADSL Address matched (Slave mode).

This bit is set by hardware as soon as the received slave address matched with the

OAR register content or a general call is recognized. An interrupt is generated if ITE=1.

It is cleared by software reading SR1 register or by hardware when the interface is

disabled (PE=0).

The SCL line is held low while ADSL=1.

0: Address mismatched or not received

1: Received address matched

Bit 1 = M/SL Master/Slave.

This bit is set by hardware as soon as the interface is in Master mode (writing

START=1). It is cleared by hardware after detecting a Stop condition on the bus or a

loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0).

0: Slave mode

1: Master mode

Bit 0 = SB Start bit (Master mode).

This bit is set by hardware as soon as the Start condition is generated (following a write

START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1

hardware when the interface is disabled (PE=0).

0: No Start condition

1: Start condition generated

I2C status register 2 (SR2)

Reset value: 0000 0000 (00h)

Bit 7:5 = Reserved.

Forced to 0 by hardware.

STOPF

ARLO

BERR

GCAL

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