ST72344S2 datasheet(125/247 Pages) STMICROELECTRONICS

125 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

125/247

11.4.7

Interrupts

Note:

The SPI interrupt events are connected to the same interrupt vector (see Section 8:

Interrupts).

They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

11.4.8

SPI control register (SPICR)

Reset value: 0000 xxxx (0xh)

Bit 7 = SPIE Serial Peripheral Interrupt Enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault

or Overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register)

Bit 6 = SPE Serial Peripheral Output Enable

This bit is set and cleared by software. It is also cleared by hardware when, in master

mode, SS = 0 (see Master mode fault (MODF)). The SPE bit is cleared by reset, so the

SPI peripheral is not initially connected to the external pins.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2 Divider Enable

This bit is set and cleared by software and is cleared by reset. It is used with the

SPR[1:0] bits to set the baud rate. Refer to Table 54: SPI master mode SCK frequency.

0: Divider by 2 enabled

1: Divider by 2 disabled

Note:

This bit has no effect in slave mode.

Table 53.

Interrupt events

Interrupt event

Event flag

Enable control

bit

Exit from Wait

Exit from Halt

SPI end of transfer event

SPIF

SPIE

Yes

Master mode fault event

MODF

Overrun error

OVR

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

Read/Write

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