ST72344S2 datasheet(124/247 Pages) STMICROELECTRONICS

124 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

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Doc ID 12321 Rev 6

Figure 62.

Single master / multiple slave configuration

11.4.6

Low-power modes

Using the SPI to wake up the device from Halt mode

In slave configuration, the SPI is able to wake up the device from Halt mode through a SPIF

interrupt. The data received is subsequently read from the SPIDR register when the

software is running (interrupt vector fetch). If multiple data transfers have been performed

before software clears the SPIF bit, then the OVR bit is set by hardware.

Note:

When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to

perform an extra communications cycle to bring the SPI from Halt mode state to normal

state. If the SPI exits from Slave mode, it returns to normal state immediately.

Caution:

The SPI can wake up the device from Halt mode only if the Slave Select signal (external SS

pin or the SSI bit in the SPICSR register) is low when the device enters Halt mode. So, if

Slave selection is configured as external (see Slave select management), make sure the

master drives a low level on the SS pin when the slave enters Halt mode.

MISO

MOSI

MISO

SCK

Slave

Device

Slave

Device

Slave

Device

Slave

Device

Master

Device

Table 52.

Description

Mode

Description

Wait

No effect on SPI.

SPI interrupt events cause the device to exit from Wait mode.

Halt

SPI registers are frozen.

In Halt mode, the SPI is inactive. SPI operation resumes when the device is woken up by

an interrupt with “exit from Halt mode” capability. The data received is subsequently read

from the SPIDR register when the software is running (interrupt vector fetching). If several

data are received before the wake-up event, then an overrun error is generated. This error

can be detected after the fetch of the interrupt routine that woke up the Device.

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