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ST72344S2 датащи(PDF) 119 Page - STMicroelectronics

номер детали ST72344S2
подробное описание детали  SCI asynchronous serial interface
PDF  247 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST72344S2 датащи(HTML) 119 Page - STMicroelectronics

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ST72344xx, ST2345xx
On-chip peripherals
Doc ID 12321 Rev 6
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Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
The SPIF bit is set by hardware.
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1.
An access to the SPICSR register while the SPIF bit is set
2.
A read to the SPIDR register
Note:
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
Write to the SPICSR register to perform the following actions:
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see Figure 60).
Note that the slave must have the same CPOL and CPHA settings as the master.
Manage the SS pin as described in Slave select management and Figure 58.
If CPHA = 1, SS must be held low continuously.
If CPHA = 0, SS must be held low during byte transmission and pulled up between
each byte to let the slave write in the shift register.
2.
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
Slave mode transmit sequence
When the software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
The SPIF bit is set by hardware.
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1.
An access to the SPICSR register while the SPIF bit is set
2.
A write or a read to the SPIDR register



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