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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72344S2 датащи(PDF) 116 Page - STMicroelectronics |
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ST72344S2 датащи(HTML) 116 Page - STMicroelectronics |
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116 / 247 page  On-chip peripherals ST72344xx, ST2345xx 116/247 Doc ID 12321 Rev 6 Figure 56. Serial peripheral interface block diagram Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure 57. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in, synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node (in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 60) but master and slave must be programmed with the same timing mode. SPIDR Read Buffer 8-bit Shift Register Write Read Data/Address Bus SPI SPIE SPE MSTR CPHA SPR0 SPR1 CPOL SERIAL CLOCK GENERATOR MOSI MISO SS SCK CONTROL STATE SPICR SPICSR Interrupt request MASTER CONTROL SPR2 0 7 0 7 SPIF WCOL MODF 0 OVR SSI SSM SOD SOD bit SS 1 0 |
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