ST72344K2 datasheet(178/247 Pages) STMICROELECTRONICS

178 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

178/247

Doc ID 12321 Rev 6

11.7.8

I2C 3S control register 1 (I2C3SCR1)

Reset value: 0000 0000 (00h)

Bits 7:6 = PL1:0 Page length configuration

This bit is set and cleared by software. It is also cleared by hardware when the interface

is disabled (PE=0).

Bit 5 = Reserved, must be kept at 0.

Bit 4 = ITER BERR / NACK Interrupt enable

This bit is set and cleared by software. It is also cleared by hardware when the interface

is disabled (PE=0).

0: BERR / NACK interrupt disabled

1: BERR / NACK interrupt enabled

Note:

In case of error, if ITER is enabled either interrupt 1 or 2 is generated depending on which

slave flags the error (see Figure 83).

Bit 3= ITRE3 Interrupt enable on read from Slave 3

This bit is set and cleared by software. It is also cleared by hardware when the interface

is disabled (PE =0).

0: Interrupt on Read from Slave 3 disabled

1: Interrupt on Read from Slave 3 enabled

Bit 2 = ITRE1/2 Interrupt enable on read from Slave 1 or 2

This bit is set and cleared by software. It is also cleared by hardware when the interface

is disabled.

(PE =0)

0: Interrupt on Read from Slave 1 or 2 disabled

1: Interrupt on Read from Slave 1 or 2 enabled

PL1

PL0

ITER

ITRE3

ITRE1/2

ITWE3

ITWE

1/2

Read / Write

Table 70.

PL configuration

PL1

PL0

Page length

Full Page (256 bytes for slave 1 & 2, 128 bytes for slave 3)

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