ST72344K2 datasheet(180/247 Pages) STMICROELECTRONICS

180 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

180/247

Doc ID 12321 Rev 6

Bit 1 = BusyW Busy on Write to RAM Buffer

This bit is set by hardware when a Stop/ Restart is detected after a write operation. The

I2C3S peripheral is temporarily disabled till this bit is reset. This bit is cleared by

software. If this bit is not cleared before the next slave address reception, further

communication will be non-acknowledged. This bit is set to 1 when modifying any bits

in Control Register 2. Writing a 1 to this bit does not actually modify BusyW but

prevents accidentally clearing of the bit.

0: No BusyW event occurred

1: A Stop/ Restart is detected after a write operation

Bit 0 = B/W Byte / Word Mode

This control bit must be set by software before a word is updated in the RAM buffer and

cleared by hardware after completion of the word update. In Word mode the CPU

cannot be interrupted when it is modifying the LSB byte and MSB byte of the word. This

mode is to ensure the coherency of data stored as words.

0: Byte mode

1: Word mode

Note:

When the word mode is enabled, all interrupts should be masked while the word is being

written in RAM.

I2C3S status register (I2C3SSR)

Reset value: 0000 0000 (00h)

Bit 7= NACK Non Acknowledge not followed by Stop

This bit is set by hardware when a non acknowledge returned by the master is not

followed by a Stop or Restart condition. It is cleared by software reading the SR register

or by hardware when the interface is disabled (PE=0).

0: No NACK error occurred

1: Non Acknowledge not followed by Stop

Bit 6 = BERR Bus error

This bit is set by hardware when the interface detects a misplaced Start or Stop

condition. It is cleared by software reading SR register or by hardware when the

interface is disabled (PE=0).

The SCL line is not held low while BERR=1.

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

Bit 5 = WF3 Write operation to Slave 3

This bit is set by hardware on reception of the direction bit in the I2C address byte for

Slave 3. This bit is cleared when the status register is read and there is no

communication ongoing or when the peripheral is disabled (PE = 0)

0: No write operation to Slave 3

1: Write operation performed to Slave 3

NACK

BERR

WF3

WF2

WF1

RF3

RF2

RF1

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