ST72344K2 datasheet(174/247 Pages) STMICROELECTRONICS

174 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

174/247

Doc ID 12321 Rev 6

When the memory address limit is reached the current address will roll over and the

sequential read will continue till the addressing master sends a stop condition. Refer to

Figure 81.

Combined format

If a master wants to continue communication either with another slave or by changing the

direction of transfer then the master would generate a restart and provide a different slave

address or the same slave address with the R/W bit reversed. Refer to Figure 82.

Rollover handling

The RAM buffer of each slave is divided into pages whose length is defined according to

PL1:0 bits in I2C3SCR1. Rollover takes place in these pages as described below.

In the case of Page Write, if the number of data bytes transmitted is more than the page

length, the current address will roll over to the first byte of the current page and the previous

data will be overwritten. This page size is configured using PL[1:0] bit in the I2C3SCR1

In case of Sequential Read, if the current address register value reaches the memory

address limit the address will roll over to the first address of the reserved area for the

respective slave.

There is no status flag to indicate the roll over.

Note:

The reserved areas for slaves 1 and 2 have a limit of 256 bytes. The area for slave 3 is 128

bytes. The MSB of the address is hardwired, the addressing master therefore needs to send

only an 8 bit address.

The page boundaries are defined based on the page size configuration using PL[1:0] bit in

the I2C3SCR1 register. If an 8-byte page size is selected, the upper 5 bits of the RAM

address are fixed and the lower 3 bits are incremented. For example, if the page write starts

at register address 0x0C, the write will follow the sequence 0x0C, 0x0D, 0x0E, 0x0F, 0x08,

0x09, 0x0A, 0x0B. If a 16-byte page size is selected, the upper 4 bits of the RAM address

are fixed and the lower 4 bits are incremented. For example, if the page write starts at

0x01, etc.

Error conditions

●

BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the

BERR bit is set by hardware with an interrupt if ITER is set. During a stop condition, the

interface discards the data, releases the lines and waits for another Start condition.

However, a BERR on a Start condition will result in the interface discarding the data

and waiting for the next slave address on the bus.

●

NACK: Detection of a non-acknowledge bit not followed by a Stop condition. In this

case, NACK bit is set by hardware with an interrupt if ITER is set.

ST72344K2 датащи(PDF) 174 Page - STMicroelectronics

ST72344K2 датащи(HTML) 174 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL