PC97338 datasheet(155/221 Pages) NSC

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Non-Extended Mode

The function of EIR is the same as in the 16550. It re-

turns an encoded value representing the highest pri-

ority pending interrupt. While a CPU access is

occurring, the module records new interrupts, but it

does not change the currently encoded value until the

access is complete. Table 75 shows the interrupt pri-

orities and the EIR encoded values.

FIGURE 88. Event Identification Register,

Non-Extended Mode

TABLE 75. Non-Extended Mode Interrupt Priorities

Extended Mode

The EIR register does not return an encoded value

like in the non-extended mode. Each bit represents an

event flag and is set to 1 when the corresponding

event occurred or is pending, regardless of the setting

of the corresponding bit in the IER register. Bit 4 is

cleared when this register is read if an 8237 type DMA

controller is used. All other bits are cleared when the

corresponding interrupts are acknowledged.

Reset

Required

IPR1

FEN0

FEN1

IPF

IPR0

RXFT

Reserved

IPF – Interrupt Pending Flag.

When this bit is 0, an interrupt is pending.

When it is 1, no interrupt is pending.

B2–1 IPR [1–0] – Interrupt Priority.

When bit 0 is 0, these bits identify the highest

priority pending interrupt.

RXFT – RX_FIFO Time-out.

In the 16450 mode this bit is always 0.

In the 16550 mode (FIFOs enabled), this bit is

set when an RX_FIFO time-out occurred and

the associated interrupt is currently the highest

priority pending interrupt.

B5–4 These bits always return 0.

B7–6 FEN [1–0] – FIFOs Enabled.

These bits are set to 1 when the FIFOs are en-

abled (bit 0 of FCR set to 1).

EIR

Bits

3 2 1 0

Priority

Level

Interrupt

Type

Interrupt Source

Interrupt Reset Control

0 0 0 1

N/A

None

N/A

0 1 1 0

Highest

Link Status Parity error, framing error, data over-run

or break event

Reading LSR Register

0 1 0 0

Second

Receiver

High-Data-

Level Event

Receiver Holding Register (RXD) full, or

RX_FIFO level equal to or above

threshold

Reading the RXD port, or

RX_FIFO level drops below

threshold

1 1 0 0

Second

RX_FIFO

Time-Out

At least one character in RX_FIFO, and

no character has been input to or read

from the RX_FIFO for 4 character times

Reading the RXD port

0 0 1 0

Third

Transmitter

Low-Data-

Level Event

Transmitter Holding Register or

TX_FIFO empty

Reading the EIR Register if this

interrupt is currently the highest

priority pending interrupt, or

writing into the TXD port

0 0 0 0

Fourth

Modem

Status

Any transition on CTS, DSR, or DCD, or

a low-to-high transition on RI

Reading the MSR Register

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