PC97338 datasheet(140/221 Pages) NSC

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FIGURE 85. CNFGB Register Bitmap

Bits 1,0 - DMA Select Bits

These bits reflect the value of bits 2 and 1 of the

SCF1 configuration register. Microsoft’s ECP Pro-

tocol and ISA Interface Standard defines these

bits shown in Table 69.

Note that bits 2-1 of SCF1 are read/write bits but

CNFGB bits are read only.

Upon reset, these bits are initialized to 00.

TABLE 69. ECP Mode DMA Selection

Bit 2 - Reserved

This bit is reserved and is always 0.

Bits 5-3 - Interrupt Select Bits

These bits reflect the value of bits 2-0 of the PNP0

configuration register. Microsoft’s ECP Protocol

and ISA Interface Standard defines these bits as

shown in Table 70.

Bits 2-0 of PNP0 are normal read/write bits but

CNFGB bits are read only.

Upon reset, these bits have an undefined value.

TABLE 70. ECP Mode Interrupt Selection

Bit 6 - IRQ Signal Value

This bit holds the value of the configured IRQ sig-

nal. The value of this bit will be undetermined if the

interrupt is not correctly configured on configura-

tion register PNP0, bits 1 and bits 7-4.

Bit 7 - Reserved

This bit is reserved and is always 0.

4.4.14 Extended Control Register (ECR),

Offset 402h

This register controls the ECP and parallel port func-

tions. On reset this register is initialized to 00010101.

IOCHRDY is driven low on ECR read when the ECR

status bits do not hold updated data.

FIGURE 86. ECR Register Bitmap

Bit 0 - FIFO Empty

This bit continuously reflects the FIFO state, and

therefore can only be read. Data written to this bit

is ignored.

When the ECP clock is frozen this bit is read as 1,

regardless of the actual FIFO state.

0 - The FIFO has at least one byte of data.

Bit 1 Bit 0

DMA Configuration

8-bit DMA selected by jumpers.

(Default)

DMA channel 1 selected.

DMA channel 2 selected.

DMA channel 3 selected.

654

Reset

Required

Configuration Register B

(CNFGB)

Offset 401h

Reserved

Interrupt Select

IRQ Signal Value

Reserved

DMA Channel Select

Bits 7-5 of ECR = 111

Bit 5 Bit 4 Bit 3

Interrupt Selection

Jumper selection.

001

IRQ7 selected.

010

IRQ9 selected.

IRQ10 selected.

IRQ11 selected.

IRQ14 selected.

IRQ15 selected.

111

IRQ5 selected.

654

Reset

Required

Extended Control

(ECR)

Offset 402h

ECP Service

ECP Interrupt Mask

ECP Mode Control

ECP DMA Enable

FIFO Full

All ECP Modes

FIFO Empty

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