PC97338 datasheet(142/221 Pages) NSC

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4.5

ECP MODE DESCRIPTIONS

4.5.1

Software Controlled Data Transfer

(Modes 000 and 001)

Software controlled data transfer is supported in

modes 000 and 001. The software generates periph-

eral-device cycles by modifying the DATAR and DCR

registers and reading the DSR, DCR and DATAR reg-

isters. The negotiation phase and nibble mode trans-

fer, as defined in the IEEE 1284 standard, are

performed in these modes.

In these modes the FIFO is reset (empty) and is not

functional, the DMA and RLE are idle.

Mode 000 is for the forward direction only; the direc-

tion bit (DCR Bit 5) is forced to 0 and PD7-0 are driv-

en. Mode 001 is for both the forward and backward

directions. The direction bit controls whether or not

pins PD7-0 are driven.

4.5.2

Automatic Data Transfer

(Modes 010 and 011)

Automatic data transfer (ECP cycles generated by

hardware) is supported only in modes 010 and 011

(Parallel Port and ECP FIFO modes). Automatic DMA

access to fill or empty the FIFO is supported in modes

010, 011 and 110. Mode 010 is for the forward direc-

tion only; the direction bit is forced to 0 and PD7-0 are

driven. Mode 011 is for both the forward and reverse

directions. The direction bit controls whether PD7-0

are driven.

Automatic Run Length Expanding (RLE) is supported

in the reverse direction.

Forward Direction (bit 5 of DCR=0)

When the ECP is in forward direction and the FIFO is

not full (bit 1 of ECR is 0) the FIFO can be filled by

software writes to the FIFO registers (AFIFO and

DFIFO in mode 011, and CFIFO in mode 010).

When DMA is enabled (bit 3 of ECR is 1 and bit 2 of

ECR is 0) the ECP automatically issues DMA re-

quests to fill the FIFO with data bytes (not including

command bytes).

When the ECP is in forward direction and the FIFO is

not empty (bit 0 of ECR is 0) the ECP pops a byte from

the FIFO and issues a write signal to the peripheral

device. The ECP drives AFD according to the opera-

tion mode (bits 7-5 of ECR) and according to the tag

of the popped byte as follows: In Parallel Port FIFO

mode (mode 010) AFD is controlled by bit 1 of DCR.

In ECP mode (mode 011) AFD is controlled by the

popped tag. AFD is driven high for normal data bytes

and driven low for command bytes.

ECP (Forward) Write Cycle

An ECP write cycle starts when the ECP drives the

popped tag onto AFD and the popped byte onto

PD7-0. When BUSY is low the ECP asserts STB. In

010 mode the ECP deasserts STB to terminate the

write cycle. In 011 mode the ECP waits for BUSY to

be high.

When BUSY is high, the ECP deasserts STB, and

changes AFD and PD7-0 only after BUSY is low.

FIGURE 87. ECP Forward Write Cycle

Reverse Direction (Bit 5 of DCR is 1)

When the ECP is in the reverse direction, and the

FIFO is not full (bit 1 of ECR is 0), the ECP issues a

read cycle to the peripheral device and monitors the

BUSY signal. If BUSY is high the byte is a data byte

and it is pushed into the FIFO. If BUSY is low the byte

is a command byte. The ECP checks bit 7 of the com-

mand byte, if it is high the byte is ignored, if it is low

the byte is tagged as an RLC byte (not pushed into

the FIFO but used as a Run Length Count to expand

the next byte read). Following an RLC read the ECP

issues a read cycle from the peripheral device to read

the data byte to be expanded. This byte is considered

a data byte, regardless of its BUSY state (even if it is

low). This byte is pushed into the FIFO (RLC+1) times

(e.g. for RLC=0, push the byte once. For RLC=127

push the byte 128 times).

When the ECP is in the reverse direction, and the

FIFO is not empty (bit 0 of ECR is 0), the FIFO can be

emptied by software reads from the FIFO register

(true only for the TFIFO in mode 011, not for AFIFO

or CFIFO reads).

When DMA is enabled (bit 3 of ECR is 1 and bit 2 of

ECR is 0) the ECP automatically issues DMA re-

quests to empty the FIFO (only in mode 011).

ECP (Reverse) Read Cycle

An ECP read cycle starts when the ECP drives AFD

low.

The peripheral device drives BUSY high for a normal

data read cycle, or drives BUSY low for a command

read cycle, and drives the byte to be read onto PD7-0.

BUSY

STB

PD7-0

AFD

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