PC97338 datasheet(143/221 Pages) NSC

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When ACK is asserted the ECP drives AFD high.

When AFD is high the peripheral device deasserts

ACK. The ECP reads the PD7-0 byte, then drives

AFD low. When AFD is low the peripheral device may

change BUSY and PD7-0 states in preparation for the

next cycle

FIGURE 88. ECP (Reverse) Read Cycle

Notes:

1. FIFO-full condition is checked before every ex-

panded byte push.

2. Switching from modes 010 or 011 to other modes

removes pending DMA requests and aborts pend-

ing RLE expansion.

3. FIFO pushes and pops are neither synchronized

nor linked at the hardware level. The FIFO will not

delay these operations, even if performed concur-

rently. Care must be taken by the programmer to

utilize the empty and full FIFO status bits to avoid

corrupting PD7-0 or D7-0 while a previous FIFO

port access not complete.

4. In the forward direction, the empty bit is updated

when the ECP cycle is completed, not when the

last byte is popped from the FIFO (valid cleared on

cycle end).

5. ZWS is not asserted for DMA cycles.

6. The one-bit command/data tag is used only in the

forward direction.

7. The DRQ (DMA Request) signal is always deas-

serted for a minimum of 330

µs after, at most, 32

consecutive DMA acess cycles.

8. If the FDC, UART, and UIR are not enabled (FER

Configuration Register) after power-up, the ECP

clock is blocked. To enable the ECP clock, set

PCR bit 3 (ECP Clock Freeze Control) to enable

ECP mode, or set the FER register bit 3 (FDC En-

able) and then reset it.

4.5.3

FIFO Test Access (Mode 110)

Mode 110 is for testing the FIFO in PIO and DMA cy-

cles. Both read and write operations (pop and push)

are supported, regardless of the direction bit.

In the forward direction PD7-0 are driven, but the data

is undefined. This mode can be used to measure the

system-ECP cycle throughput, usually with DMA cy-

cles. This mode can also be used to check the FIFO

depth and its interrupt threshold, usually with PIO cy-

cles.

4.5.4

Configuration Registers Access

(Mode 111)

The two configuration registers, CNFGA and CNFGB,

are accessible only in this mode.

4.5.5

Interrupt Generation

An interrupt is generated according to bit 5 and 6 set-

ting in the PCR, when any of the events described in

this section occurs. Interrupt events 2, 3 and 4 are lev-

el events. They are shaped as interrupt pulses, and

are masked (inactive) when the ECP clock is frozen.

Event 1

Bit 2 of ECR is 0, bit 3 of ECR is 1 and TC is as-

serted during ECP DMA cycle. Interrupt event 1 is

a pulse event.

Event 2

Bit 2 of ECR is 0, bit 3 of ECR is 0, bit 5 of DCR is

0 and there are eight or more bytes free in the

FIFO.

This event includes the case when bit 2 of ECR is

cleared to 0 and there are already eight or more

bytes free in the FIFO (modes 010, 011 and 110

only).

Event 3

Bit 2 of ECR is 0, bit 3 of ECR is 0, bit 5 of DCR is

1 and there are eight or more bytes to be read from

the FIFO.

This event includes the case when bit 2 of ECR is

cleared to 0 and there are already eight or more

bytes to be read from the FIFO (modes 011 and

110 only).

Event 4

Bit 4 of ECR is 0 and ERR is asserted (high to low

edge) or ERR is asserted when bit 4 of ECR is

modified from 1 to 0.

This event may be lost when the ECP clock is fro-

zen.

Event 5

When bit 4 of DCR is 1 and ACK is deasserted

(low-to-high edge).

This event behaves as in the normal SPP mode,

i.e., the IRQ signal follows the ACK signal transi-

tion (when bit 5 of PCR is 0 and bit 6 of PCR is 0).

PD7-0

BUSY

AFD

ACK

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