20

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6

Internal use, do not overwrite.

5

Internal use, do not overwrite.

4

Internal use, do not overwrite.

3

Internal use, do not overwrite.

2

Internal use, do not overwrite.

1

Internal use, do not overwrite.

0

X-Bus Warm Start

Write only: 0 = NOP; 1 = Execute system wide reset (used only for clock configuration at power-up)

Index 45h-4Fh

Internal use, do not overwrite

Index 50h

ISA CLK Divider (R/W)

Reset Value = 43h

7

Internal use, do not overwrite.

6

Internal use, do not overwrite.

5

Internal use, do not overwrite.

4

Internal use, do not overwrite.

3

Internal use, do not overwrite.

2:0

ISA Clock Divisor — Determines the divisor of the PCI clock used to generate the ISA bus clock:

010 = Divide by three (ISA clock = 11MHz)

011 = Divide by four (ISA clock = 8.33 MHz)

All other values are invalid and can produce unexpected results.

Index 51h

ISA I/O Recovery Control Register (R/W)

Reset Value = 43h

7:4

8-Bit I/O Recovery — These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read

cycles. This count is in addition to a preset one-clock delay built into the controller.

0000 = 1 PCI clock1101 = 14 PCI clocks

0001 = 2 PCI clocks1110 = 15 PCI clocks

:::1111 = 16 PCI clocks

3:0

16-Bit I/O Recovery — These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O

cycles. This count is in addition to a preset one-clock delay built into the controller.

0000 = 1 PCI clock1101 = 14 PCI clocks

0001 = 2 PCI clocks1110 = 15 PCI clocks

:::1111 = 16 PCI clocks

Index 52h

ROM Control Register (R/W)

Reset Value = 04h

7

Internal use, do not overwrite.

6

Internal use, do not overwrite.

5

Internal use, do not overwrite.

4

Internal use, do not overwrite.

3

Internal use, do not overwrite.

2

ROM 1MB Enable — Allow addressing to 512K or 1MB ROM (FFF00000h-FFFFFFFFh):

0 = Disable; 1 = Enable.

1

Internal use, do not overwrite.

0

Internal use, do not overwrite.

Table 4. Bridge Configuration Registers (Continued)

Bit

Description