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5.0 Pin Descriptions

5.1 Signal Definitions

This section defines the signals and describes the external interface of the PC87200. The following diagram shows the

pins organized by their functional groupings. Internal test and electrical pins are not shown.

AD[31:0]

C/BE[3:0]#

PAR

FRAME#

TRDY#

STOP#

DEVSEL#

SERR#

IDSEL

SERIRQ

PCI Bus

IRQ Interface

IRDY#

PCICLK

SYSCLK

Clocks

Reset

PCIRST#

PC87200

SA[23:0]

IOCHK#

SBHE#

BALE

IOCHRDY

REFRESH#

IOR#

IOW#

MEMCS16#

MEMR#

MEMW#

AEN

DREQ[7:5], [3:0]

DACK#[7:5], [3:0]

TC

IRQ[15:14], [12:9], [7:3]

ISA Bus

IOCS16#

SD[15:0]

SMEMW#

SMEMR#

Serialized

PROHIBIT

MASTER#

BPD#

RSTDRV

PC87200 Signal Groups

PCPCIGNT#

PCPCIREQ#

Enhanced Integrated PCI-to-ISA

Bridge