PC87200 datasheet(3/33 Pages) NSC

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3.0 Device Overview

The PC87200 can be described as providing the functional

blocks shown in Figure 1.

— PCI bus master/slave interface

— ISA bus master/slave interface

— Serial IRQ slave mode interface

— PROHIBIT signal support

— PC/PCI DMA interface

3.1 PCI Bus Interface

The PC87200 provides a PCI bus interface that is both a

slave for PCI cycles initiated by the CPU or other PCI mas-

ter devices, and a PC/PCI DMA master for DMA transfer

cycles. The PC87200 supports positive decode for the

BIOS ROM in the special test mode and implements sub-

tractive decode for unclaimed PCI accesses when the

PROHIBIT signal is low. The PC87200 also generates

address and data parity and performs parity checking.

Conﬁguration registers are accessed through the PCI inter-

face using the PCI Bus Type 1 conﬁguration mechanism as

described in the PCI 2.1 Speciﬁcation.

3.2 ISA Bus Interface

The PC87200 provides an ISA bus interface for subtrac-

tive-decoded memory and I/O cycles on PCI. The

PC87200 is the default subtractive decoding agent and will

forward all unclaimed memory and I/O cycles to the ISA

interface; however, the PC87200 may be conﬁgured to

ignore either I/O, memory or all unclaimed cycles (subtrac-

tive decode disabled) by asserting the PROHIBIT signal.

ISA master cycles will only be passed to the PCI bus if they

access memory. I/O accesses are left to complete on the

ISA bus.

ISA master cycles that access memory on ISA bus are not

supported by the PC87200.

3.3 Serialized IRQ support

The PC87200’s Serial Interrupt interface uses a serial

interrupt bus to transmit ISA Bus legacy interrupt requests.

The bus is a one pin bus (SERIRQ) and uses the PCI clock

as its timing reference. The serial interrupt bus is a multi-

drop bus that is shared by all PCI devices that have legacy

interrupts. The serial interrupt logic conforms to the serial-

ized IRQ deﬁned in the Serialized IRQ on the “PCI way” -

Version 6.0 speciﬁcation. Programming of the serial inter-

rupt controller when the controller is currently running can

produce unexpected results.

X-Bus

ISA Bus

PCI Bus

PCI to X-Bus / X-Bus to PCI Bridge

PCI Conﬁguration

Registers

X-Bus Arbiter

PC87200 Support

Serial IRQ Slave

mode interface logic

Serialized IRQ

Interface

PC/PCI DMA

Interface

ISA bus Target

Interface

ISA bus Master

Interface

PCPCIREQ#

PCPCIGNT#

Decoding logic

BPD#

PROHIBIT

Internal Block Diagram

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