PC87200 datasheet(5/33 Pages) NSC

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3.0 Device Overview (Continued)

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3.4 PROHIBIT signal support

The chipset will use this signal to claim the BIOS ﬁrst and

then deassert the "PROHIBIT" signal to conﬁgure the PCI

to ISA bridge to continue the boot sequence.

Special test mode support is provided by means of the

BPD# pin. When this test mode is active, the PC87200 will

enable positive memory decode during boot up to enable

the host to look for boot ROM on ISA card.

PROHIBIT will be a don’t care in this test mode at boot up

for the ROM BIOS range, but should function normally after

booting

3.5 PC/PCI DMA Interface Support

The PC87200 operates as a PC/PCI DMA Secondary Arbi-

tration Bridge. The PC87200 can pass all seven legacy ISA

bus DMA channel requests to the PC/PCI DMA Primary

Bus Arbiter using the channel passing protocol deﬁned in

the Moble PC/PCI DMA Arbitration and Protocol Speciﬁca-

tion (Revision 2.2). Figure 1 shows the topology of the

PC87200 PC/PCI DMA requests and grants:

The PC87200 converts the seven legacy ISA bus DMA

requests (DREQ0, 1, 2, 3, 5, 6 and 7) into a serial PC/PCI

DMA compliant REQ# sequence and converts the corre-

sponding PC/PCI DMA GNT# sequence into the appropri-

ate DMA acknowledge (DACK0-3, 5-7#). This PC/PCI DMA

expansion

Channel

Passing

Protocol

illustrated

Figure 2.

Table 1. SERIRQ Slave Generation Periods

SERIRQ

Period

Signal Generated

# of clocks past

Start

Reserved.

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

Reserved.

IRQ9

IRQ10

IRQ11

IRQ12

Reserved.

IRQ14

IRQ15

IOCHK#

21:18

Reserved.

62,59,56, 53

Figure 1. PC87200 PC/PCI DMA Topology

Figure 2. Channel Passing Protocol

PC/PCI DMA

Primary Bus

Arbiter

PCI Bus

PCPCIREQ#

PCPCIGNT#

PC87200

PC/PCI DMA Interface Support

ISA Bus

start

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

start

bit 0

bit 1

bit 2

PCICLK

PCPCIREQ

PCPCIGNT#

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