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Index 41h

PCI Function Control Register 2 (R/W)

Reset Value = 10h

7

Burst to Beat — Bursts are converted to single beats for X-Bus to PCI bus reads: 0 = Disable; 1 = Enable.

6

Internal use, do not overwrite

5

PERR# Signals SERR# — Assert SERR# any time that PERR# is asserted or detected active by the

PC87200 (allows PERR# assertion to be cascaded to NMI (SMI) generation in the system): 0 = Disable; 1 =

Enable.

4

Write Buffer Enable — Allow 16-byte buffering for X-Bus to PCI bus writes: 0 = Disable; 1 = Enable.

3

Internal use, do not overwrite.

2:1

Subtractive Decode — These bits determine the point at which the PC87200 accepts cycles that are not

claimed by another device. The PC87200 defaults to taking subtractive decode cycles in the default cycle

clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or me-

dium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded

subtractively.

00 = Default sample (4th clock from FRAME# active)

01 = Slow sample (3rd clock from FRAME# active)

1x = No subtractive decode

0

Internal use, do not overwrite.

Index 42h

PCI Function Control Register 3 (R/W)

Reset Value = 28h

7

Internal use, do not overwrite

6

Internal use, do not overwrite.

5

Delayed Transactions — Allow delayed transactions on the PCI bus: 0 = Disable; 1 = Enable.

4

Internal use, do not overwrite.

3

No X-Bus ARB, Buffer Enable — When PC87200 is a PCI target, allow buffer PCI transactions without X-Bus

arbitration: 0 = Disable; 1 = Enable.

2

Internal use, do not overwrite.

1

Internal use, do not overwrite.

0

Internal use, do not overwrite.

Index 43h

PCI Function Control Register 4

Reset Value = 46h

7

Reserved — Set to 0.

6

Internal use, do not overwrite.

5

Internal use, do not overwrite.

4

Internal use, do not overwrite.

3

Internal use, do not overwrite.

2

Internal use, do not overwrite.

1

PCI Retry Cycles — When PC87200 is a PCI target and the PCI buffer is not empty, allow PCI bus to retry

cycles:

0 = Disable; 1 = Enable.

This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be

valid.

0

Internal use, do not overwrite.

Index 44h

Reset Control Register (R/W)

Reset Value = 00000000b

7

Internal use, do not overwrite.

Table 4. Bridge Configuration Registers (Continued)

Bit

Description