ADP1050ACPZ-R7 datasheet(79/93 Pages) AD

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ADP1050

Data Sheet

Table 118. Register 0xFE1F—CS1 Cycle-by-Cycle Current-Limit Settings

Bits

Bit Name/Function

R/W

Description

CS1 cycle-by-cycle current-

limit comparator ignored

R/W

Setting this bit causes the CS1 OCP comparator output to be ignored. The CS1_OCP internal

flag is always cleared.

[6:4]

Leading edge blanking

R/W

These bits determine the leading edge blanking time. During this time, the CS1 OCP comparator

output is ignored. This time is measured from the rising edges of OUTA and OUTB

(programmable in Register 0xFE1D[1:0]).

Bit 6

Bit 5

Bit 4

Leading Edge Blanking Time (ns)

120

200

400

600

800

[3:2]

Reserved

R/W

Reserved.

[1:0]

CS1 cycle-by-cycle

current-limit

debounce time

R/W

These bits set the CS1 cycle-by-cycle current-limit debounce time. This is the minimum time

that the CS1 signal must be constantly above the CS1 cycle-by-cycle current-limit reference

before the PWM outputs are shut down. When this happens, the selected PWM outputs can

be disabled for the remainder of the switching cycle.

Bit 1

Bit 0

Debounce Time (ns)

120

VOLTAGE SENSE AND LIMIT SETTING REGISTERS

Table 119. Register 0xFE20—VS Gain Trim

Bits

Bit Name/Function

R/W

Description

Trim polarity

R/W

0 = positive gain is introduced.

1 = negative gain is introduced.

[6:0]

VS gain trim

R/W

These bits set the amount of gain trim that is applied to the VS ADC reading. This register trims the

voltage reading in the READ_VOUT command after the VOUT_CAL_OFFSET trimming is completed.

This register is trimmed until the READ_VOUT reading in the register exactly matches the output

voltage measurement result.

Table 120. Register 0xFE25—Prebias Start-Up Enable

Bits

Bit Name/Function

R/W

Description

Prebias startup

enable

R/W

Setting this bit enables the prebias start-up function. If it is enabled, the soft start ramp starts from the

current output voltage. The initial PWM modulation value is generated based on the following: the

initial modulation calculation, set Register 0xFE6C[1] = 1, unless closed-loop input voltage

feedforward operation mode is in use.

[6:0]

Reserved

R/W

Reserved.

Table 121. Register 0xFE26—VOUT_OV_FAULT Flag Debounce

Bits

Bit Name/Function

R/W

Description

[7:6]

VOUT_OV_FAULT

flag debounce

R/W

These bits set the VOUT_OV_FAULT flag debounce time.

Bit 7

Bit 6

Typical Debounce Time (μs) (Delay Time 1)

[5:0]

Reserved

R/W

Reserved

Rev. A | Page 78 of 92

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