ADP1050ACPZ-R7 datasheet(75/93 Pages) AD

75 / 93 page

ADP1050

Data Sheet

Table 105. Register 0xFE0C—Volt-Second Balance Blanking and SR Disable During Soft Start

Bits

Bit Name/Function

R/W

Description

[7:5]

Reserved

R/W

Reserved.

VIN_UV_FAULT reenable blank

R/W

0 = VIN_UV_FAULT flag is not blanked during the flag reenable delay. This is the

recommended setting if the input voltage signal can be sensed by the ADP1050 before the

PSU starts to operate.

1 = VIN_UV_FAULT flag is blanked during the flag reenable delay.

First flag ID update

R/W

This bit specifies whether the first flag ID is saved in the EEPROM. If it is set, the first flag ID

is saved in the EEPROM. During the VDD power reset, the first flag ID is downloaded from

the EEPROM to Register 0xFEA6.

0 = the first flag ID is not saved in the EEPROM.

1 = the first flag ID is saved in the EEPROM.

Flag shutdown timing

R/W

Specifies when the PWM outputs are shut down after a manufacturer specific flag is triggered.

0 = the PWM outputs are shut down at the end of the switching cycle.

1 = the PWM outputs are shut down immediately.

Volt-second balance blanking

R/W

0 = the volt-second balance control is not blanked during soft start.

1 = the volt-second balance control is blanked during soft start.

SR disable

R/W

0 = SR1 and SR2 are not disabled during soft start.

1 = SR1 and SR2 are disabled during soft start.

Table 106. Register 0xFE0D—PGOOD Mask Settings

Bits

Bit Name/Function

R/W

Description

VIN_UV_FAULT flag

R/W

1 = the VIN_UV_FAULT flag is ignored by PGOOD.

IIN_OC_FAST_FAULT flag

R/W

1 = the IIN_OC_FAST_FAULT flag is ignored by PGOOD.

Reserved

R/W

Reserved.

VOUT_OV_FAULT flag

R/W

1 = the VOUT_OV_FAULT flag is ignored by PGOOD.

VOUT_UV_FAULT flag

R/W

1 = the VOUT_UV_FAULT flag is ignored by PGOOD.

OT_FAULT flag

R/W

1 = the OT_FAULT flag is ignored by PGOOD.

OT_WARNING flag

R/W

1 = the OT_WARNING flag is ignored by PGOOD.

Reserved

R/W

Reserved.

Table 107. Register 0xFE0E—PGOOD Flag Debounce

Bits

Bit Name/Function

R/W

Description

[7:6]

Reserved

R/W

Reserved.

CS1 cycle-by-cycle current limit

to disable OUTB

R/W

Setting this bit enables the CS1 cycle-by-cycle current limit to disable the OUTB output for the

remainder of the switching cycle when cycle-by-cycle current limiting occurs.

CS1 cycle-by-cycle current limit

to disable OUTA

R/W

Setting this bit enables the CS1 cycle-by-cycle current limit to disable the OUTA output

for the remainder of the switching cycle when cycle-by-cycle current limiting occurs.

[3:2]

PGOOD flag clearing debounce

R/W

These bits specify the PGOOD flag clearing debounce, which is the time from when

the PGOOD clearing condition is met to the time when the PGOOD flag is cleared.

Bit 3

Bit 2

PGOOD Flag Setting Debounce (ms)

200

320

600

[1:0]

PGOOD flag setting debounce

R/W

These bits specify the PGOOD flag setting debounce, which is the time from when

the PGOOD setting condition is met to the time when the PGOOD flag is set and the

PG/ALT pin is pulled low.

Bit 1

Bit 0

PGOOD Flag Clearing Debounce (ms)

200

320

600

Rev. A | Page 74 of 92

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