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978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com

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0

0 - 24

HMC700LP4 / 700LP4E

v11.0411

8 GHz 16-Bit Fractional-N PLL

Table 20. Reg 0Dh GPO_SPI_RDIV Register

Bit

name

Width

Default

Description

[3:0]

gpo_select

4

10d

test signals selected here are output to gpo pins when

D1 & D0

0: clk_vcodiv & clk_refdiv

1: pfd_up & pfd_dn

2: refout & refDivout

3: seed_stb_sypulse_test & frac_stb_sypulse_test

4: intg_inbuff_enable_test & clk_sd

5: oneshot_trigg_test & oneshot_pulse_test

6: ‘0’ & ringosc_test

7: csp_corr_add & csp_corr_sub

8: pfd_sat_refdiv & pfd_sat_vcodiv

9: (csp_corr_add or csp_corr_sub) & pfd_sat_rstb

10: gpo_test , see reg0D<5:4>

11: not used

12: not used

13: not used

14: not used

15: not used

[5:4]

gpo_test

2

0

data written to this register is output to D0 and D1 pins when gpo_select = 10d

[6]

refclkdiv4

1

0

1: sel ref divby4 for clocking the vco_spi

0: sel ref divby1 for clocking the vco_spi

[7]

to_gpo_sdo

1

0

enable the automatic output of vcospi_vco_data to LD_SDo

output Vco_SPi clock to D1 (see Reg0D<6>)

output Vco_SPi En to D0

Table 21. Reg 0Fh LD State Register (Read Only)

Bit

name

Width

Default

Description

[0]

locked

1

0

read only Lock Detect flag, 1 when locked

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