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HMC700LP4 / 700LP4E

v11.0411

8 GHz 16-Bit Fractional-N PLL

RF Path ’N’ Divider

Charge Pump and Phase Frequency Detector

the Phase Frequency Detector or PFD has two inputs, one from the reference path divider and one from the rF path

divider. When in lock these two inputs are at the same average frequency and are fixed at a constant average phase

compares the phase of the rF path signal with that of the reference path signal and controls the charge pump output

current as a linear function of the phase difference between the two signals. the output current varies linearly over a

full ±2π radians input phase difference.

PFD Test Functions

detector, to allow for negative slope Vco or inverting op-amp in the loop filter.

from pumping up.

from pumping down.

De-asserting both pfd_up_en and pfd_dn_en effectively tri-states the charge pump while leaving all other

functions operating internally.

PFD Jitter and Lock Detect Background

in normal phase locked operation the divided Vco signal arrives at the phase detector in phase with the divided

crystal signal, known as the PFD reference signal. Despite the fact that the device is in lock, the phase of the Vco

signal and the PFD reference signal vary in time due to the phase noise of the reference and Vco oscillators, the loop

bandwidth used and the presence of fractional modulation or not. the total integrated noise from the Vco normally

dominates the variations in the two arrival times at the phase detector in integer mode.

if we wish to detect if the Vco is in lock or not we need to distinguish between normal phase jitter when in lock and

phase jitter when not in lock.

First, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional

modes.

the standard deviation of the arrival time of the Vco signal, or the jitter, in integer mode may be estimated with a

the loop 3 dB bandwidth and a 20 dB per decade rolloff at greater offsets. the simple locked Vco phase noise

approximation is shown in Figure 10.

Figure 10. Synthesizer Phase Noise & Jitter

B

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