For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com

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0

0 - 16

HMC700LP4 / 700LP4E

v11.0411

8 GHz 16-Bit Fractional-N PLL

a. Digital clocks

b. internal bias reference sources

c. PFD block

d. charge Pump Block

e. reference Path buffer

f. Vco Path buffer

g. Digital i/o test pads

Chip Identification

the version of the synthesizer is described in Table 6. Version information may be read from the synthesizer by

reading the content of chip_ID in reg 00h.

SERIAL PORT

typical serial port operation can be run with ScK at speeds up to 50MHz.

Serial Port WRITE Operation

Table 4. Timing Characteristics

Parameter

conditions

Min

typ

Max

Units

SEn to ScK Setup time

8

nsec

SDi to ScK Setup time

5

nsec

SDi to ScK Setup time

5

nsec

tsck

ScK period

20

nsec

ScK High Duration

8

nsec

ScK Low Duration

8

nsec

SEn High Duration

640

nsec

SEn Low Duration

20

nsec

a typical WritE cycle is shown in Figure 15.

a. the Master (host) both asserts SEn (Serial Port Enable) and clears SDi to indicate a WritE cycle,

followed by a rising edge of ScK.

b. the slave (synthesizer) reads SDi on the 1st rising edge of ScK after SEn. SDi low initiates the Write

cycle (/Wr).

c. Host places the six address bits on the next six falling edges of ScK, MSB first.

d. Slave registers the address bits in the next six rising edges of ScK (2-7).

e. Host places the 24 data bits on the next 24 falling edges of ScK, MSB first .

f. Slave registers the data bits on the next 24 rising edges of ScK (8-31).

g. SEn is de-asserted on the 32nd falling edge of ScK.

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