HMC700LP4 datasheet(10/26 Pages) AD

10 / 26 page

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HMC700LP4 / 700LP4E

v11.0411

8 GHz 16-Bit Fractional-N PLL

PFD Jitter and Lock Detect Background (Continued)

in summary, the lock detect circuit must not interpret fractional modulation or normal phase noise related jitter as

being out of lock, while at the same time declaring loss of lock when truly out of lock.

PFD Lock Detect

lkd_enable in table 14 enables the lock detect functions of the HMc700LP4(E).

the Lock Detect circuit in the HMc700LP4(E) places a one shot window around the reference. the one shot window

may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator.

clearing ringosc_oneshot_sel (table 14) will result in a fixed analog based nominal 10 nsec window, as shown in

Figure 11. Setting ringosc_oneshot_sel will result in a variable length widow based upon a high frequency internal ring

oscillator. the ring oscillator frequency is controlled by ringosc_cfg. the resulting lock detect window period is then

generated by the number of ring oscillator periods defined in oneshot_duration, both in (table 14).

wincnt_max in table 14 defines the number of consecutive counts of the divided Vco that must land inside the lock

detect window to declare lock. if for example we set wincnt_max = 1000 , then the Vco arrival would have to occur

inside the ±10 nsec widow 1000 times in a row to be declared locked, which results in a Lock Detect Flag high. a single

occurrence outside of the window will result in an out of lock, i.e. Lock Detect Flag low. once low, the Lock Detect Flag

will stay low until the wincnt_max =1000 condition is met again.

the Lock Detect Flag is output to LD_SDo pin according to pfd_LD_opEn (table 18) or to the internal SPi read only

serial port read is requested, in which case the pin reverts temporarily to the Serial Data out pin, and returns to the

Lock Detect Flag after the read is completed. timing of the Lock Detect and Serial Data out functions are shown in

Figure 11.

Figure 11. Normal Lock Detect Window

When operating in fractional mode the linearity of the charge pump and phase detector are much more critical than in

integer mode. the phase detector linearity is worse when operated with zero phase offset. Hence in fractional mode

it is necessary to offset the phase of the PFD reference and the Vco at the phase detector. in such a case, for

example with an offset delay, as shown in Figure 12, the Vco arrival will always occur after the reference. the

lock detect circuit can accommodate a fixed offset delay by setting lkd_win_asym_enable and win_asym_up_sel in

table 14. Similarly the offset can be in advance of the reference by clearing lkd_win_asym_up_sel while leaving

lkd_win_asym_enable set both in table 14. there are certain conditions, such as operating near the supply limits of

the charge pump which make it advantageous to use advanced or delayed phase offset, hence both are available.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

Phone: 781-329-4700 • Order online at www.analog.com

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