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HMC700LP4 / 700LP4E

v11.0411

8 GHz 16-Bit Fractional-N PLL

Reference Input Stage

the reference input provides the path from the external reference source to the phase detector. the input stage of the

reference path is shown in Figure 8. HMc700LP4(E) is a Dc coupled, common emitter differential nPn buffer. input

pins have 1.8V bias on them. Expected input is full swing 3V cMoS. Slightly degraded phase noise performance may

result with quasi sine or sine inputs. input reference should have a noise floor better than -155 dBc/Hz at 50MHz to

avoid degradation of the input reference path. the input reference path phase noise floor is approximately equivalent to

-155 dBc/Hz. this input should be well isolated from the Vco for best spurious performance in fractional mode.

Figure 8. Reference Path Input Stage

Ref Path ’R’ Divider

the reference path “r” divider is based on a 14 bit counter and can divide input signals of up to 220 MHz input by

RF Input Stage

the rF input stage provides the path from the external Vco to the phase detector via the fractional divider. the rF

input path is rated to operate nominally from 100 MHz to 8 GHz. the HMc700LP4(E) rF input stage is a differential

common emitter stage with Dc coupling, and is protected by ESD diodes as shown in Figure 9. the rF input stage is

internally matched from a single ended 50 ohm source above about 3.5 GHz, with the complimentary input grounded.

if a better match is required at low frequency a simple shunt 50ohm resistor can be used external to the package.

the rF input stage has excellent sensitivity (see figure 4). Excessive drive levels can result in more coupling and

spurious products in fractional mode. -10 dBm is a recommended drive level.

Figure 9. RF Input Stage

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