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HMC700LP4 / 700LP4E

v11.0411

8 GHz 16-Bit Fractional-N PLL

Table 13. Reg 06h SD CFG Register

Bit

name

Width

Default

Description

[7:0]

reserved

87h

[9:8]

order

2

2h

Select the Modulator type

0 - not used

1 - not used

2 - type B

3 - type a

[10]

frac_rstb

1

1

0 holds the frac core in reset

reset is used for integer mode or integer mode with cSP

[11]

buff_rstb

1

1

0 holds the frac core buffers in reset

reset is used with frac_rstb=0 for integer mode, no cSP

[12]

bypass_mode

1

0

1 fractional modulator output is ignored, but fractional modulator

continues to be clocked, used to test the isolation of the

digital fractional modulator from the Vco output in integer

mode

[13]

autoseed_mode

1

1

loads the seed whenever the frac register is written

[14]

reserved

1

0

Must be kept at 0

[15]

fsk_enable

1

0

enables the FSK mode of operation and FSK input on SDi

pin, (see section FSK Modulation)

[16]

reserved

1

0

[17]

clkrq_refdiv_sel

1

0

selects the SD clock source

1 = reference divider clock

0 = Vco divider clock (recommended)

[18]

clkrq_invert_clk

1

1

inverts the selected sd clock

[19]

sd_spare_out

1

0

spare

[23:20]

csp_corr_magn

4

8h

cSP magnitude correction (see section cycle Slip Prevention (cSP))

0000 low magnitude

1111 high magnitude

sign of the correction is determined automatically by the cSP state machine

note: to Enable Frac Mode:

Set reg 6 [12:10]= 011

also, reg 9[9:7] or reg 9[4:2] must be adjusted to mitigate spurs in frac mode (Dn or Up Leakage)

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