ADF4356BCPZ datasheet(29/35 Pages) AD

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Data Sheet

ADF4356

Rev. 0 | Page 29 of 35

M14

M13

..........

MOD2_MSB VALUE

..........

16380

..........

16381

..........

16382

.........

16383

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_MSB)

CONTROL

BITS

M14

M13

M12

M11

M10

C3(1) C2(0) C1(1)

C4(1)

DBR

F14

F13

..........

FRAC2_MSB WORD

..........

16381

..........

16382

..........

16382

.........

16383

F11

F10

F12

F13

F14

14-BIT AUXILIARY FRACTIONAL MSB VALUE (FRAC2_LSB)

1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 41. Register 13

Control Bits

With [C4:C1] set to 1101, Register 13 is programmed. Figure 41

shows the input data format for programming this register.

14-Bit Auxiliary Fractional MSB Value (FRAC2_MSB)

This value is used with the auxiliary fractional LSB value

(Register 2, Bits[DB31:DB18]) to generate the total auxiliary

fractional FRAC2 value.

FRAC2 = (FRAC2_MSB × 214) + FRAC2_LSB

These bits can be set to all zeros to ensure software

compatibility with the ADF4355.

14-Bit Auxiliary Modulus MSB Value (MOD2_MSB)

This value is used with the auxiliary fractional MSB value

(Register 2, Bits[DB17:DB4]) to generate the total auxiliary

modulus MOD2 value.

MOD2 = (MOD2_MSB × 214) + MOD2_LSB

At initial power-up, after the correct application of voltages to

the supply pins, the ADF4356 registers must be programmed in

sequence. For f ≤ 75 MHz, use the following sequence:

1. Register 13.

2. Register 12.

3. Register 11.

4. Register 10.

5. Register 9.

6. Register 8.

7. Register 7.

8. Register 6.

9. Register 5.

10. Register 4.

11. Register 3.

12. Register 2.

13. Register 1.

14. Ensure that >16 ADC_CLK cycles have elapsed between

the write of Register 10 and Register 0. For example, if

ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs. See

the Register 10 section for more information.

15. Register 0.

For fPFD > 75 MHz (initially lock with halved fPFD), use the

following sequence:

1. Register 13 (for halved fPFD).

2. Register 12.

3. Register 11.

4. Register 10.

5. Register 4 (with the R divider doubled to halve fPFD).

6. Register 9.

7. Register 8.

8. Register 7.

9. Register 6 (for the desired fPFD).

10. Register 5.

11. Register 4 (with the R divider doubled to halve fPFD).

12. Register 3.

13. Register 2 (for halved fPFD).

14. Register 1 (for halved fPFD).

15. Ensure that >16 ADC_CLK cycles have elapsed between

the write of Register 10 and Register 0. For example, if

ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs. See the

16. Register 0 (for halved fPFD; autocalibration enabled).

17. Register 13 (for the desired fPFD).

18. Register 4 (with the R divider set for the desired fPFD).

19. Register 2 (for the desired fPFD).

20. Register 1 (for the desired fPFD).

21. Register 0 (for the desired fPFD; autocalibration disabled).

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