ADF4356BCPZ datasheet(20/35 Pages) AD

20 / 35 page

ADF4356

Data Sheet

Rev. 0 | Page 20 of 35

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

DB12

DB13

DB14

DB15

DB16

DB17

DB18

DB19

DB20

DB21

DB22

DB23

DB24

DB25

DB26

DB27

DB28

DB29

DB30

DB31

C1(1)

C2(1)

C3(0)

C4(0)

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

PA1

PR1

SD1

DBR1

24-BIT PHASE VALUE (PHASE)

CONTROL

BITS

PHASE VALUE (PHASE)

....

P23

P24

....

16777212

....

16777213

....

16777214

....

16777215

1DBR = DOUBLE BUFFERED REGISTER–BUFFERED BY THE WRITE TO REGISTER 0.

....

PA1

DISABLED

ENABLED

PHASE

ADJUST

PR1

DISABLED

ENABLED

PHASE

RESYNC

SD1

ON REGISTER0 UPDATE

DISABLED

SD LOAD

RESET

Figure 31. Register 3

Control Bits

With Bits[C4:C1] set to 0011, Register 3 is programmed. Figure 31

shows the input data format for programming this register.

Reserved

Bit DB31 is reserved and must be set to 0.

SD Load Reset

When writing to Register 0, the Σ-Δ modulator resets. For

applications in which the phase is continually adjusted, this may

not be desirable; therefore, in these cases, the Σ-Δ reset can be

disabled by writing a 1 to the SD1 bit (Bit DB30).

Phase Resync

To use the phase resynchronization feature, the PR1 bit (Bit DB29)

must be set to 1. If unused, the bit can be programmed to 0. The

phase resync activation timeout value must also be used in

after the PLL settles to the final frequency. If the PLL has not settled

to the final frequency, phase resync may not function correctly.

Resynchronization is useful in phased array and beam forming

applications. It ensures repeatability of output phase when

programming the same frequency. In phase critical applications

that use frequencies requiring the output divider (<3400 MHz),

it is necessary to feed the N divider with the divided VCO

frequency as distinct from the fundamental VCO frequency,

which is achieved by programming the D13 bit (Bit DB24) in

For resync applications, enable the Σ-Δ modulator load reset

(SD load reset) in Register 3 by setting DB30 to 0.

The phase of the RF output frequency can be adjusted in 24-bit

steps from 0° (0) to 360° (224 − 1) relative to the resync phase.

For phase adjustment applications, the phase is set by Bits[P24:P1].

(Phase Value/16,777,216) × 360°

Practically, this means that repeatable adjustable phase values can

be achieved by using the resync feature with different phase values.

Phase Adjustment

To adjust the relative output phase of the ADF4356 on each

differs from the resynchronization feature in that it is useful when

adjustments to phase are made continually in an application.

For this function, disable the VCO automatic calibration by

setting the AC1 bit (Bit DB21) in Register 0 to 1, and disable the

SD load reset by setting the SD1 bit (Bit DB30) in Register 3 to 1.

24-Bit Phase Value

The phase of the RF output frequency can adjust in 24-bit steps,

from 0° (0) to 360° (224 − 1). For phase adjust applications, the

phase is set by

(Phase Value/16,777,216) × 360°

When the phase value is programmed to Register 3, each

subsequent adjustment of Register 0 increments the phase by

the value in this equation.

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