ADF4356BCPZ datasheet(8/35 Pages) AD

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ADF4356

Data Sheet

Rev. 0 | Page 8 of 35

Pin No.

Mnemonic

Description

VTUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT

output voltage. The capacitance at this pin (VTUNE input capacitance) is 9 pF.

NIC

No Internal Connection. For existing designs that currently use the ADF4355, to upgrade to the ADF4356, the

RSET resistor can be left connected to this pin.

VREF

Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the

ground plane as close to this pin as possible.

VBIAS

Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.

25, 32

CREG1, CREG2

Outputs from the LDO Regulator. CREG1 and CREG2 are the supply voltages to the digital circuits. Nominal

voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.

PDBRF

RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software-controllable.

Do not leave this pin floating.

DVDD

Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground

plane as close to this pin as possible.

REFINB

Complementary Reference Input. If unused, ac couple this pin to AGND.

REFINA

Reference Input.

MUXOUT

Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or

the scaled reference frequency to be externally accessible.

SDGND

Digital Σ-Δ Modulator Ground. SDGND is the ground return path for the Σ-Δ modulator.

Exposed Pad. The exposed pad must be connected to AGND.

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