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ADF4356BCPZ датащи(PDF) 19 Page - Analog Devices

номер детали ADF4356BCPZ
подробное описание детали  6.8 GHz Wideband Synthesizer with Integrated VCO
PDF  35 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADF4356BCPZ датащи(HTML) 19 Page - Analog Devices

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Data Sheet
ADF4356
Rev. 0 | Page 19 of 35
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
DB18
DB19
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB28
DB29
DB30
DB31
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
0
0
0
0
C1(1)
C2(0)
C3(0)
C4(0)
RESERVED
DBR1
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
CONTROL
BITS
MAIN FRACTIONAL VALUE (FRAC1)
F1
F12
....
F23
F24
0
0
0
....
0
0
1
1
0
....
0
0
2
0
1
....
0
0
3
1
1
....
0
0
.
.
.
....
.
.
.
.
.
....
.
.
.
.
.
....
.
.
16777212
0
0
....
1
1
16777213
1
1
....
1
1
16777214
1
1
....
1
1
16777215
1DBR = DOUBLE BUFFERED REGISTER–BUFFERED BY THE WRITE TO REGISTER 0.
1
1
....
1
1
Figure 29. Register 1
FRAC2_LSB WORD
F1
F2
....
F13
F14
0
0
0
....
0
0
1
1
0
....
0
0
2
0
1
....
0
0
3
1
1
....
0
0
.
.
.
....
.
.
.
.
.
....
.
.
.
.
.
....
.
.
16381
0
0
....
1
1
16382
1
0
....
1
1
16382
0
1
....
1
1
16383
1DBR = DOUBLE BUFFERED REGISTER–BUFFERED BY THE WRITE TO REGISTER 0.
1
1
....
1
1
MOD2_LSB VALUE
M1
M2
....
M13
M14
NOT ALLOWED
0
0
....
0
0
NOT ALLOWED
1
0
....
0
0
2
0
1
....
0
0
3
1
1
....
0
0
.
.
.
....
.
.
.
.
.
....
.
.
.
.
.
....
.
.
16380
0
0
....
1
1
16381
1
0
....
1
1
16382
0
1
....
1
1
16383
1
1
....
1
1
14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_LSB)
14-BIT AUXILIARY FRACTIONAL LSB VALUE (FRAC2_LSB)
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
DB18
DB19
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB28
DB29
DB30
DB31
C1(0)
C2(1)
C3(0)
C4(0)
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
CONTROL
BITS
Figure 30. Register 2
REGISTER 1
Control Bits
With Bits[C4:C1] set to 0001, Register 1 is programmed. Figure 29
shows the input data format for programming this register.
Reserved
Bits[DB31:DB28] are reserved and must be set to 0.
24-Bit Main Fractional Value
The 24 FRAC1 bits (Bits[DB27:DB4]) set the numerator of the
fraction that is input to the Σ-Δ modulator. This fraction, along
with the INT value, specifies the new frequency channel that
the synthesizer locks to, as shown in the RF Synthesizer—A
Worked Example section. FRAC1 values from 0 to (MOD1 − 1)
cover channels over a frequency range equal to the PFD
reference frequency.
REGISTER 2
Control Bits
With Bits[C4:C1] set to 0010, Register 2 is programmed. Figure 30
shows the input data format for programming this register.
14-Bit Auxiliary Fractional LSB Value (FRAC2_LSB)
Use this value with the auxiliary fractional MSB value (Register 13,
Bits[DB31:DB18]) to generate the total auxiliary fractional value.
FRAC2 = (FRAC2_MSB × 214) + FRAC2_LSB
FRAC2 must be less than the MOD2 value programmed in
Register 2.
14-Bit Auxiliary Modulus LSB Value (MOD2_LSB)
Use this value with the auxiliary modulus MSB value (Register 13,
Bits[DB17:DB4]) to generate total auxiliary modulus value.
MOD2 = (MOD2_MSB) × 214 + MOD2_LSB
Use MOD2 to correct any residual error due to the main
fractional modulus.



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