ADF4356BCPZ datasheet(7/35 Pages) AD

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Data Sheet

ADF4356

Rev. 0 | Page 7 of 35

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. NIC = NOT INTERNALLY CONNECTED.

2. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

VBIAS

VREF

NIC

AGNDVCO

VTUNE

VREGVCO

AGNDVDO

VVCO

CLK

DATA

AVDD

CPOUT

CPGND

ADF4356

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

CLK

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

DATA

Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four LSBs as the control bits.

This input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register

that is selected by the four LSBs.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.

A logic high on this pin powers up the device, depending on the status of the power-down bits.

5, 16

AVDD

Analog Power Supplies. These pins range from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog

ground plane as close to these pins as possible. AVDD must have the same value as DVDD.

Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the

ground plane as close to this pin as possible.

CPOUT

Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the

loop filter is connected to VTUNE to drive the internal VCO.

CPGND

Charge Pump Ground. This output is the ground return pin for CPOUT.

AGND

Analog Ground. This pin is the ground return pin for AVDD.

VRF

Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this

pin as possible. VRF must have the same value as AVDD.

RFOUTA+

VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is

available.

RFOUTA−

Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided

down version is available.

AGNDRF

RF Output Stage Ground. This pin is the ground return pin for the RF output stage.

RFOUTB+

Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down

version is available.

RFOUTB−

Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a

divided down version is available.

VVCO

Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Place decoupling capacitors to

the analog ground plane as close to this pin as possible.

18, 21

AGNDVCO

VCO Ground. This pin is the ground return path for the VCO.

VREGVCO

VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.

Connect VREGVCO directly to VVCO.

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