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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADF4356BCPZ датащи(PDF) 18 Page - Analog Devices |
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ADF4356BCPZ датащи(HTML) 18 Page - Analog Devices |
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18 / 35 page  ADF4356 Data Sheet Rev. 0 | Page 18 of 35 16-BIT INTEGER VALUE (INT) DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DB18 DB19 DB20 DB21 DB22 DB23 DB24 DB25 DB26 DB27 DB28 DB29 DB30 DB31 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N1 INTEGER VALUE (INT) N2 N3 N4 N5 .... N15 N16 0 NOT ALLOWED 0 0 0 0 .... 0 0 1 NOT ALLOWED 0 0 0 0 .... 0 0 0 NOT ALLOWED 1 0 0 0 .... 0 0 ..... . . . . .... . . 0 NOT ALLOWED 1 1 0 1 .... 0 0 123 1 1 0 1 .... 0 0 024 0 0 1 1 .... 0 0 ..... . . . . .... . . 1 65533 0 1 1 1 .... 1 1 0 65534 1 1 1 1 .... 1 1 1 65535 INTMIN = 75 WITH PRESCALER = 8/9 1 1 1 1 .... 1 1 PR1 PR1 0 1 4/5 8/9 PRESCALER AC1 0 0 0 0 0 0 0 0 0 0 C1(0) C2(0) C3(0) C4(0) RESERVED CONTROL BITS AC1 0 1 DISABLED DISABLED VCO AUTOCAL Figure 28. Register 0 REGISTER 0 Control Bits With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 28 shows the input data format for programming this register. Reserved Bits[DB31:DB22] are reserved and must be set to 0. Automatic Calibration (AUTOCAL) Write to Register 0 to enact (by default) the VCO automatic calibration, and to choose the appropriate VCO and VCO subband. Write 1 to the AC1 bit (Bit DB21) to enable the automatic calibration, which is the recommended mode of operation. Set the AC1 bit (Bit DB21) to 0 to disable the automatic calibration, which leaves the ADF4356 in the same band it was already in when Register 0 is updated. Disable the automatic calibration only for fixed frequency applications, phase adjust applications, or very small (<10 kHz) frequency jumps. Toggling AUTOCAL is also required when changing frequency. See the Frequency Update Sequence section for more information. Prescaler Value The dual modulus prescaler (P/P + 1), along with the INT, FRACx, and MODx counters, determines the overall division ratio from the VCO output to the PFD input. The PR1 bit (Bit DB20) in Register 0 sets the prescaler value. Operating at CML levels, the prescaler takes the clock from the VCO output and divides it down for the counters. It is based on a synchronous 4/5 core. When the prescaler is set to 4/5, the maximum RF frequency allowed is 7 GHz. The prescaler limits the INT value; therefore, if P is 4/5, NMIN is 23, and if P is 8/9, NMIN is 75. 16-Bit Integer Value The 16 INT bits (Bits[DB19:DB4]) set the INT value, which determines the integer part of the feedback division factor. The INT value is used in Equation 3 (see the INT, FRACx, MODx, and R Counter Relationship section). All integer values from 23 to 32,767 are allowed for the 4/5 prescaler. For the 8/9 prescaler, the minimum integer value is 75, and the maximum value is 65,535. |
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