LAN8741AI-EN datasheet(17/106 Pages) MICROCHIP

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DS00001988A-page 17

LAN8741A/LAN8741Ai

3.1.1.3

Scrambling

Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band

peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire

channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being

radiated by the physical wiring.

The seed for the scrambler is generated from the transceiver address, PHYAD, ensuring that in multiple-transceiver

applications, such as repeaters or switches, each transceiver will have its own scrambler sequence.

The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.

3.1.1.4

NRZI and MLT-3 Encoding

The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125 MHz NRZI

data stream. The NRZI is encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents a

code bit “1” and the logic output remaining at the same level represents a code bit “0”.

3.1.1.5

100M Transmit Driver

The MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on outputs TXP and

TXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10BASE-T and 100BASE-TX signals pass

through the same transformer so that common “magnetics” can be used for both. The transmitter drives into the 100 Ω

impedance of the CAT-5 cable. Cable termination and impedance matching require external components.

3.1.1.6

100M Phase Lock Loop (PLL)

The 100M PLL locks onto reference clock and generates the 125 MHz clock used to drive the 125 MHz logic and the

100BASE-TX transmitter.

3.1.2

100BASE-TX RECEIVE

The 100BASE-TX receive data path is shown in Figure 3-2. Each major block is explained in the following subsections.

FIGURE 3-2:

100BASE-TX RECEIVE DATA PATH

MAC

A/D

Converter

MLT-3

Converter

NRZI

Converter

4B/5B

Decoder

Magnetics

CAT-5

RJ45

PLL

MII 25 MHz by 4 bits

RMII 50 MHz by 2 bits

RX_CLK

(for MII only)

25 MHz by

5 bits

NRZI

MLT-3

6 bit Data

Descrambler

and SIPO

125 Mbps Serial

DSP: Timing

recovery, Equalizer

and BLW Correction

MLT-3

MII/RMII

25 MHz

by 4 bits

Ext Ref_CLK (for RMII only)

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