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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN8741Ai-EN датащи(PDF) 92 Page - Microchip Technology |
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LAN8741Ai-EN датащи(HTML) 92 Page - Microchip Technology |
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92 / 106 page  LAN8741A/LAN8741Ai DS00001988A-page 92 2013-2015 Microchip Technology Inc. 5.6.4 RMII INTERFACE TIMING This section specifies the RMII interface transmit and receive timing. Note 1: Timing was designed for system load between 10 pF and 25 pF. Note: The CRS_DV pin performs both carrier sense and data valid functions. CRS_DV is asserted asynchro- nously on detection of carrier due to the criteria relevant to the operating mode. If the PHY has additional bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, then the device will assert CRS_DV on cycles of REF_CLK which present the second di-bit of each nibble and deassert CRS_DV on cycles of REF_CLK which present the first di-bit of a nibble. For additional information, refer to the RMII specification. FIGURE 5-6: RMII TIMING TABLE 5-12: RMII TIMING VALUES Symbol Description Min. Typ. Max. Unit Note tclkp CLKIN period 20 ns tclkh CLKIN high time tclkp * 0.35 tclkp * 0.65 ns tclkl CLKIN low time tclkp * 0.35 tclkp * 0.65 ns toval RXD[1:0], RXER, CRS_DV output valid from rising edge of CLKIN 15.0 ns (see Note 1) toinvld RXD[1:0], RXER, CRS_DV output invalid from rising edge of CLKIN 3.0 ns (see Note 1) tsu TXD[1:0], TXEN setup time to ris- ing edge of CLKIN 4.0 ns (see Note 1) tihold TXD[1:0], TXEN input hold time after rising edge of CLKIN 1.5 ns (see Note 1) tclkh tclkl tclkp toval toinvld toval toval toinvld tsu tihold tsu tihold tihold tsu tihold CLKIN (REF_CLK) (INPUT) RXD[1:0], RXER (OUTPUTS) CRS_DV (OUTPUT) TXD[1:0] (INPUTS) TXEN (INPUT) |
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