LAN8741AI-EN datasheet(28/106 Pages) MICROCHIP

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LAN8741A/LAN8741Ai

DS00001988A-page 28

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3.6

Interrupt Management

The device management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. This

interrupt capability generates an active low asynchronous interrupt signal on the nINT output whenever certain events

are detected as setup by the Interrupt Mask Register.

The device’s interrupt system provides two modes, a Primary interrupt mode and an Alternative interrupt mode. Both

systems will assert the nINT pin low when the corresponding mask bit is set. These modes differ only in how they de-

assert the nINT interrupt output. These modes are detailed in the following subsections.

3.6.1

PRIMARY INTERRUPT SYSTEM

The Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status Register is “0”). The

Primary interrupt system is always selected after power-up or hard reset. In this mode, to set an interrupt, set the cor-

responding mask bit in the Interrupt Mask Register (see Table 3-3). Then when the event to assert nINT is true, the nINT

output will be asserted. When the corresponding event to deassert nINT is true, then the nINT will be de-asserted.

Note 1: If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high, nINT will assert

for 256 ms, approximately one second after ENERGYON goes low when the Cable is unplugged. To prevent

an unexpected assertion of nINT, the ENERGYON interrupt mask should always be cleared as part of the

ENERGYON interrupt service routine.

Note:

The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternative

interrupt mode requires setup after a power-up or hard reset.

TABLE 3-3:

INTERRUPT MANAGEMENT TABLE

Mask

Interrupt Source Flag

Interrupt Source

Event to Assert

nINT

Event to

De-Assert nINT

30.7

29.7

ENERGYON

17.1

ENERGYON

Rising 17.1 (see

Note 1)

Falling 17.1 or

Reading register 29

30.6

29.6

Auto-Negotiation

Complete

1.5

Auto-Negotiate

Complete

Rising 1.5

Falling 1.5 or

Reading register 29

30.5

29.5

Remote Fault

Detected

1.4

Remote Fault

Rising 1.4

Falling 1.4, or

Reading register 1 or

Reading register 29

30.4

29.4

Link Down

1.2

Link Status

Falling 1.2

Reading register 1 or

Reading register 29

30.3

29.3

Auto-Negotiation

LP Acknowledge

5.14

Acknowledge

Rising 5.14

Falling 5.14 or

Reading register 29

30.2

29.2

Parallel Detection

Fault

6.4

Parallel Detec-

tion Fault

Rising 6.4

Falling 6.4 or

Reading register 6, or

Reading register 29, or

Re-Auto Negotiate or

Link down

30.1

29.1

Auto-Negotiation

Page Received

6.1

Page Received

Rising 6.1

Falling 6.1 or

Reading register 6, or

Reading register 29, or

Re-Auto Negotiate, or

Link down.

Note:

The ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the signal acqui-

sition process, therefore the INT7 bit in the Interrupt Mask Register will also read as a ‘1’ at power-up. If no

signal is present, then both ENERGYON and INT7 will clear within a few milliseconds.

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