LAN8741AI-EN datasheet(35/106 Pages) MICROCHIP

35 / 106 page

 2013-2015 Microchip Technology Inc.

DS00001988A-page 35

LAN8741A/LAN8741Ai

When in EDPD mode, the device’s NLP characteristics may be modified. The device can be configured to transmit NLPs

in EDPD via the EDPD TX NLP Enable bit of the EDPD NLP/Crossover Time/EEE Configuration Register. When

enabled, the TX NLP time interval is configurable via the EDPD TX NLP Interval Timer Select field of the EDPD

NLP/Crossover Time/EEE Configuration Register. When in EDPD mode, the device can also be configured to wake on

the reception of one or two NLPs. Setting the EDPD RX Single NLP Wake Enable bit of the EDPD NLP/Crossover

Time/EEE Configuration Register will enable the device to wake on reception of a single NLP. If the EDPD RX Single

NLP Wake Enable bit is cleared, the maximum interval for detecting reception of two NLPs to wake from EDPD is con-

figurable via the EDPD RX NLP Max Interval Detect Select field of the EDPD NLP/Crossover Time/EEE Configuration

3.8.4

ENERGY EFFICIENT ETHERNET

The device supports IEEE 802.3az Energy Efficient Ethernet (EEE). The EEE functionality is enabled/disabled via the

PHY Energy Efficient Ethernet Enable (PHYEEEEN) bit of the EDPD NLP/Crossover Time/EEE Configuration Register.

Energy Efficient Ethernet is disabled by default. In order for EEE to be utilized, the following conditions must be met:

• The device must configured in MII mode (RMIISEL configuration strap low)

• The nINT/TXER/TXD4 pin must be configured as TXER/TXD4 (nINTSEL configuration strap low)

• EEE functionality must be enabled via the PHY Energy Efficient Ethernet Enable (PHYEEEEN) bit of the EDPD

NLP/Crossover Time/EEE Configuration Register

•The 100BASE-TX EEE bit of the MMD EEE Advertisement Register must be set

• The selected MAC and link-partner must support and be configured for EEE operation

• The device and link-partner must link in 100BASE-TX full-duplex mode

The value of the PHY Energy Efficient Ethernet Enable (PHYEEEEN) bit affects the default values of the following reg-

ister bits:

• 100BASE-TX EEE bit of the MMD EEE Capability Register

• 100BASE-TX EEE bit of the MMD EEE Advertisement Register

3.8.5

ISOLATE MODE

The device data paths may be electrically isolated from the MII/RMII interface by setting the Isolate bit of the Basic Con-

trol Register to “1”. In isolation mode, the transceiver does not respond to the TXD, TXEN and TXER inputs, but does

respond to management transactions.

Isolation provides a means for multiple transceivers to be connected to the same MII/RMII interface without contention.

By default, the transceiver is not isolated (on power-up (Isolate =0).

3.8.6

RESETS

The device provides two forms of reset: hardware and software. The device registers are reset by both hardware and

software resets. Select register bits, indicated as “NASR” in the register definitions, are not cleared by a software reset.

The registers are not reset by the power-down modes described in Section 3.8.3.

3.8.6.1

Hardware Reset

A hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held low for the minimum

time detailed in Section 5.6.2, "Power-On nRST & Configuration Strap Timing" to ensure a proper transceiver reset.

During a hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal.

Note:

EEE cannot be used in RMII mode.

Note:

For the first 16 µs after coming out of reset, the MII/RMII interface will run at 2.5 MHz. After this time, it will

switch to 25 MHz if auto-negotiation is enabled.

Note:

A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.6.2, "Power-On

nRST & Configuration Strap Timing" for additional information.

LAN8741Ai-EN датащи(PDF) 35 Page - Microchip Technology

LAN8741Ai-EN датащи(HTML) 35 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL