LAN8741AI-EN datasheet(9/106 Pages) MICROCHIP

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DS00001988A-page 9

LAN8741A/LAN8741Ai

Receive Error

RXER

VO8

This signal is asserted to indicate that an error was

detected somewhere in the frame presently being

transferred from the transceiver. This signal is also

used in EEE mode as RXER when RXDV = 1, and

as LPI when RXDV = 0.

Note:

This signal is optional in RMII mode.

Receive

Data 4

(MII Mode)

RXD4

VO8

In Symbol Interface (5B decoding) mode, this sig-

nal is the MII Receive Data 4 signal, the MSB of the

received 5-bit symbol code-group.

Note:

Unless configured to the Symbol Inter-

face mode, this pin functions as RXER.

PHY Address 0

Configuration

Strap

PHYAD0

VIS

(PD)

Combined with PHYAD1 and PHYAD2, this config-

uration strap sets the transceiver’s SMI address.

See Note 1 for more information on configuration

straps.

Note:

Refer to Section 3.7.1, "PHYAD[2:0]:

PHY Address Configuration" for addi-

tional information.

Receive Clock

(MII Mode)

RXCLK

VO8

In MII mode, this pin is the receive clock output.

• MII (100BASE-TX): 25 MHz

• MII (10BASE-T): 2.5 MHz

PHY Address 1

Configuration

Strap

PHYAD1

VIS

(PD)

Combined with PHYAD0 and PHYAD2, this config-

uration strap sets the transceiver’s SMI address.

See Note 1 for more information on configuration

straps.

Note:

Refer to Section 3.7.1, "PHYAD[2:0]:

PHY Address Configuration" for addi-

tional information.

Receive Data

Valid

RXDV

VO8

Indicates that recovered and decoded data is avail-

able on the RXD pins.

Collision Detect

(MII Mode)

COL

VO8

This signal is asserted to indicate detection of a

collision condition in MII mode.

Carrier Sense /

Receive Data

Valid

(RMII Mode)

CRS_DV

VO8

This signal is asserted to indicate the receive

medium is non-idle in RMII mode. When a

10BASE-T packet is received, CRS_DV is

asserted, but RXD[1:0] is held low until the SFD

byte (10101011) is received.

Note:

Per the RMII standard, transmitted data

is not looped back onto the receive data

pins in 10BASE-T half-duplex mode.

PHY Operat-

ing Mode 2

Configuration

Strap

MODE2

VIS

(PU)

Combined with MODE0 and MODE1, this configu-

ration strap sets the default PHY mode.

See Note 1 for more information on configuration

straps.

Note:

Refer to Section 3.7.2, "MODE[2:0]:

Mode Configuration" for additional

details.

TABLE 2-1:

MII/RMII SIGNALS (CONTINUED)

Num Pins

Name

Symbol

Buffer Type

Description

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