PM6344 datasheet(83/256 Pages) PMC

83 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Bit

Type

Function

Default

Bit 7

R/W

PATHCRC

Bit 6

Unused

Bit 5

Unused

Bit 4

R/W

TXSA4EN

Bit 3

R/W

TXSA5EN

Bit 2

R/W

TXSA6EN

Bit 1

R/W

TXSA7EN

Bit 0

R/W

TXSA8EN

PATHCRC:

The PATHCRC bit allows upstream block errors to be preserved in the

transmit CRC bits. If PATHCRC is a logic 1, the CRC-4 bits are modified to

reflect any bit values in BTPCM[x] which have changed prior to transmission.

When PATHCRC is set to logic 0, the TRAN block is allowed to generate a

new CRC-4 value which overwrites the incoming CRC-4 word. For the

PATHCRC bit to be effective, the BTXMFP bit of the Transmit Backplane

Options register must be a logic 1; otherwise, the identification of the

incoming CRC-4 bits would be impossible. The PATHCRC bit only takes effect

if the GENCRC bit of the TRAN Configuration register (44H) is a logic 1 and

either the INDIS or FDIS bit in the same register are set to logic1.

TXSA4EN, TXSA5EN, TXSA6EN, TXSA7EN and TXSA8EN:

The TXSAxEN bits control the insertion of a data link into the Time Slot 0

National Use bits (Sa4 through Sa8).

These bits only have effect if the TRAN block Configuration DLEN bit is logic

0 or if the TRAN block Configuration SIGEN bit is logic 1. The TXSAxEN bits

take priority over the INDIS and FDIS bits of the TRAN block Configuration

If the TXDMASIG bit is a logic 1, the data link bits are sourced by the internal

HDLC transmitter; otherwise, the bits are sourced from the TDLSIG[x] pin. If

the TXSA4EN bit is logic 1, the TDLSIG[x] value is written into bit 4 of Time

Slot 0 of non-frame alignment signal frames. If the TXSA8EN bit is logic 1,

the TDLSIG[x] value is written into bit 8 of Time Slot 0 of non-frame alignment

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