PM6344 datasheet(79/256 Pages) PMC

79 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

TDPINV,TDNINV:

The TDPINV and TDNINV bits enable the E1 Transmit Interface to logically

invert the signals output on the TDP/TDD[x] and TDN/TFLG [x] multifunction

pins, respectively. When TDPINV is set to logic 1, the TDP/TDD[x] output is

inverted. When TDPINV is set to logic 0, the TDP/TDD[x] output is not

inverted. When TDNINV is set to logic 1, the TDN/TFLG[x] output is inverted.

When TDNINV is set to logic 0, the TDN/TFLG[x] output is not inverted.

TUNI:

The TUNI bit enables the transmit interface to generate unipolar digital

outputs on the TDP/TDD[x] and TDN/TFLG[x] multifunction pins. When TUNI

is set to logic 1, the TDP/TDD[x] and TDN/TFLG[x] multifunction pins become

the unipolar outputs TDD[x] and TFLG[x], updated on the selected TCLKO[x]

edge. When TUNI is set to logic 0, the TDP/TDD[x] and TDN/TFLG[x]

multifunction pins become the bipolar outputs TDP[x] and TDN[x], also

updated on the selected TCLKO[x] edge.

FIFOFULL:

The FIFOFULL bit determines the indication given on the TFLG[x] output pin.

When FIFOFULL is set to logic 1, the TFLG[x] output indicates when the

Digital Jitter Attenuator's FIFO is within 4 bit positions of becoming full.

When FIFOFULL is set to logic 0, the TFLG[x] output indicates when the

Digital Jitter Attenuator's FIFO is within 4 bit positions of becoming empty.

TRISE:

The TRISE bit configures the interface to update the multifunction outputs on

the rising edge of TCLKO[x]. When TRISE is set to logic 1, the interface is

enabled to update the TDP/TDD[x] and TDN/TFLG[x] output pins on the rising

TCLKO[x] edge. When TRISE is set to logic 0, the interface is enabled to

update the outputs on the falling TCLKO[x] edge.

TRZ:

The TRZ bit configures the interface to transmit bipolar return-to-zero

formatted waveforms. When TRZ is set to logic 1, the interface is enabled to

generate the TDP[x] and TDN[x] output signals as RZ waveforms with

duration equal to half the TCLKO[x] period. When TRZ is set to logic 0, the

interface is enabled to generate the TDP[x] and TDN[x] output signals as NRZ

waveforms with duration equal to the TCLKO[x] period, updated on the

selected edge of TCLKO[x]. The TRZ bit can only be used when TUNI and

TRISE are set to logic 0.

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