PM6344 datasheet(73/256 Pages) PMC

73 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Bit

Type

Function

Default

Bit 7

R/W

RXDMASIG

Bit 6

R/W

RFRACE1

Bit 5

R/W

TXDMASIG

Bit 4

R/W

TFRACE1

Bit 3

R/W

RDLINTE

Bit 2

R/W

RDLEOME

Bit 1

R/W

TDLINTE

Bit 0

R/W

TDLUDRE

This register allows software to configure the datalink options.

RXDMASIG:

The RXDMASIG bit selects the internal HDLC receiver (RFDL) data-received

interrupt (INT) and end-of-message (EOM) signals to be output on the

RDLINT[x] and RDLEOM[x] pins. When RXDMASIG is set to logic 1, the

RDLINT[x] and RDLEOM[x] output pins can be used by a DMA controller to

process the datalink. When RXDMASIG is set to logic 0, the RFDL INT and

EOM signals are no longer available to a DMA controller; the signals on

RDLINT[x] and RDLEOM[x] become the extracted datalink data and clock,

RDLSIG[x] and RDLCLK[x]. In this mode, the data stream available on the

RDLSIG[x] output corresponds to the extracted datalink from Time Slot 16 or

the Time Slot 0 National Use bits depending on the state of the RXSAxEN

bits of the Receive TS0 Data Link Enable register. The RFRACE1 bit takes

precedent over RXDMASIG.

RFRACE1:

The RFRACE1 bit selects whether a fractional E1 is extracted and made

available on the RDLSIG[x] output, or whether the RDLINT/RDLSIG[x] and

RDLEOM/RDLCLK[x] pins operate as defined by the RXDMASIG bit. When

RFRACE1 is set to logic 1, the contents of the Channel Select registers

determine which channels are output on RDLSIG[x] with an aligned burst

clock output on RDLCLK[x]. When RFRACE1 is set to logic 0, the

RDLINT/RDLSIG[x] and RDLEOM/RDLCLK[x] pins contain the signals

selected by the RXDMASIG bit.

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