DS3134 datasheet(144/203 Pages) DALLAS

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DS3134

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Bits 8 to 11 / Transmit DMA Configuration RAM Word Select Bits 0 to 3 (TDCW0 to TDCW3).

0000 = lower word of dword 0

0001 = upper word of dword 0

0010 = lower word of dword 1 (only word that the Host can write to)

0011 = upper word of dword 1

0100 = lower word of dword 2

0101 = upper word of dword 2

0110 = lower word of dword 3

0111 = upper word of dword 3

1000 = lower word of dword 4

1001 = upper word of dword 4

1010 = lower word of dword 5

1011 = upper word of dword 5

Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal

Transmit DMA Configuration RAM, this bit should be written to a one by the host. This causes the

device to begin obtaining the data from the channel location indicated by the HCID bits. During the read

access, the IAB bit will be set to one. Once the data is ready to be read from the TDMAC register, the

IAB bit will be set to zero.

When the host wishes to write data to the internal Transmit DMA

Configuration RAM, this bit should be written to a zero by the host. This causes the device to take the

data that is current present in the TDMAC register and write it to the channel location indicated by the

HCID bits. When the device has completed the write, the IAB bit will be set to zero.

Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only

bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be

read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set

to a one while the write is taking place. It will be set to zero once the write operation has completed.

TDMAC

0874h

5432

D15

D14

D13

D12

D11

D10

Note: Bits that are underlined are read only, all other bits are read-write.

Bits 0 to 15 / Transmit DMA Configuration RAM Data (D0 to D15). Data that is written to or read

from the Transmit DMA Configuration RAM.

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