CLC5903 datasheet(18/29 Pages) NSC

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rate of 270.833kHz. An OSP starts when a sample is ready

and stops when the next one is ready.

Serial Outputs

The CLC5903 provides a serial clock (SCK), a frame strobe

(SFS) and two data lines (AOUT and BOUT) to output serial

data. The MUX_MODE control register specifies whether the

two channel outputs are transmitted on two separate serial

pins, or multiplexed onto one pin in a time division multi-

plexed (TDM) format. Separate output pins are not provided

for the I and Q halves of complex data. The I and Q outputs

are always multiplexed onto the same serial pin. The I-com-

ponent is output first, followed by the Q-component. By set-

ting the PACKED mode bit to ‘1’ a complex pair may be

treated as a single double-wide word. The RDY signal is

used to identify the first word of a complex pair of the TDM

formatted output when the SFS_MODE bit is set to ‘0’. Set-

ting SFS_MODE to ‘1’ causes the CLC5903 to output a sin-

gle SFS pulse for each output period. This SFS pulse will be

coincident with RDY and only a single SCK period wide. The

TDM modes are summarized in Table 1.

The serial outputs use the format shown in Figure 30. Figure

30(a) shows the standard output mode (the PACKED mode

bit is low). The chip clocks the frame and data out of the chip

on the rising edge of SCK (or falling edge if the SCK_POL bit

in the input control register is set high). Data should be cap-

tured on the falling edge of SCK (rising if SCK_POL=1). The

SFS_MODE

MUX_MODE

SERIAL OUTPUTS

AOUT

BOUT

OUTA

OUTB

OUTA, OUTB LOW

OUTA

OUTB

OUTA, OUTB LOW

Table 1. TDM Modes

SCK

SFS

AOUT

I15

I14

Q15

Q14

(a) UNPACKED MODE, FRAME SYNC AT THE START OF EACH WORD

SCK

SFS

AOUT

I15

I14

Q15

Q14

(b) PACKED MODE, ONE FRAME SYNC AT THE START OF EACH DOUBLE-WORD TRANSFER

clock stops and data is zero after transfers are complete

RDY

SFS

A|BOUT

AOUT

MUX_MODE=0, SFS_MODE=0|1

MUX_MODE=1, SFS_MODE=0

Output Sample Period (OSP)

SFS

SCK

SFS

AOUT

mI7

eI3

eI0

eQ3

(d) FLOATING POINT FORMAT

eQ0

mQ0

mI0

mQ7

leading edge of RDY aligns with leading edge of SFS

Figure 30. Serial output formats. Refer to Figure 10 for detailed timing information

RDY is 2 CK periods wide

mI6

eI2

clock stops and data is zero after transfers are complete

SFS

AOUT

MUX_MODE=1, SFS_MODE=1

Output Modes (Continued)

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