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SCK will be set to the proper strobe rate for each debug tap

point. POUT_EN and PSEL[2..0] have no effect in Debug

Mode. The outputs are turned on when the Debug Mode bit

is set. Normal serial outputs are also disabled.

Control Registers

The chip is configured and controlled through the use of 8-bit

control registers. These registers are accessed for reading or

writing using the control bus pins (CE, RD, WR, A[7:0], and

D[7:0]) described in the Control Interface section.

The two sets of FIR coefficients are overlaid at the same

memory address. Use the PAGE_SEL registers to access

the second set of coefficients.

The register names and descriptions are listed below under

Control Register Addresses and Defaults on page 21. A

quick reference table is provided in the Condensed CLC5903

Address Map on page 22.

Control Register Addresses and Defaults

Register Name

Width

Type

Addr

Bit

Description

DEC

11b

R/W

7

0(LSBs)

1(MSBs)

7:0

2:0

CIC decimation control. N=DEC+1. Valid range is from 7 to 2047. Format is an unsigned

integer. This affects both channels.

DEC_BY_4

1b

R/W

0

1

4

Controls the decimation factor in F2. 0=Decimate by 2. 1=Decimate by 4. This affects both

channels.

SCALE

6b

R/W

0

2

5:0

CIC SCALE parameter. Format is an unsigned integer representing the number of left bit

shifts to perform on the data prior to the CIC filter. Valid range is from 0 to 40. This affects

both channels.

GAIN_A

3b

R/W

0

3

2:0

Value of left bit shift prior to F1 for channel A.

GAIN_B

3b

R/W

0

4

2:0

Value of left bit shift prior to F1 for channel B.

RATE

1B

R/W

1

5

7:0

Determines rate of serial output clock. The output rate is FCK/(RATE+1). Unsigned integer

values of 0, 1, 3, 7, 15, and 31 are allowed.

SOUT_EN

1b

R/W

0

6

0

Enables the serial output pins AOUT, BOUT, SCK, and SFS. 0=Tristate. 1=Enabled.

SCK_POL

1b

R/W

0

6

1

Determines polarity of the SCK output. 0=AOUT, BOUT, and SFS change on the rising

edge of SCK (capture on falling edge). 1=They change on the falling edge of SCK.

SFS_POL

1b

R/W

0

6

2

Determines polarity of the SFS output. 0=Active High. 1=Active Low.

RDY_POL

1b

R/W

0

6

3

Determines polarity of the RDY output. 0=Active High. 1=Active Low.

MUX_MODE

1b

R/W

0

6

4

Determines the mode of the serial outputs. 0=Each channel is output on its respective pin,

1=Both channels are multiplexed and output on AOUT. See also Table 1.

PACKED

1b

R/W

0

6

5

Controls when SFS goes active. 0=SFS pulses prior to the start of the I and the Q words.

1=SFS pulses only once prior to the start of each I/Q sample pair (i.e. the pair is treated as

a double-sized word) The I word precedes the Q word. See Figure 30.

FORMAT

2b

R/W

0

6

7:6

Determines output number format. 0=Truncate serial output to 8 bits. Parallel output is trun-

cated to 32 bits. 1=Round both serial and parallel to 16 bits. All other bits are set to 0.

2=Round both serial and parallel to 24 bits. All other bits are set to 0. 3=Output floating

point. 8-bit mantissa, 4-bit exponent. All other bits are set to 0.

FREQ_A

4B

R/W

0

7-10

7:0

Frequency word for channel A. Format is a 32-bit, 2’s complement number spread across 4

PHASE_A

2B

R/W

0

11-12

7:0

Phase word for channel A. Format is a 16-bit, unsigned magnitude number spread across 2

registers. The LSBs are in the lower registers. The NCO phase PHI is PHI=2*pi*PHASE_A/

2^16.

FREQ_B

4B

R/W

0

13-16

7:0

Frequency word for channel B. Format is a 32-bit, 2’s complement number spread across 4

PHASE_B

2B

R/W

0

17-18

7:0

Phase word for channel B. Format is a 16-bit, unsigned magnitude number spread across 2

registers. The LSBs are in the lower registers. The NCO phase PHI is PHI=2*pi*PHASE_B/

2^16.

A_SOURCE

2

R/W

0

19

1:0

0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel

input source.

B_SOURCE

2

R/W

1

19

3:2

0=Select AIN as channel input source. 1=Select BIN. 2=3=Select TEST_REG as channel

input source.

EXP_INH

1b

R/W

0

20

0

0=Allow exponent to pass into FLOAT TO FIXED converter. 1=Force exponent in DDC

channel to a 7 (maximum digital gain). This affects both channels.

Reserved

1b

R/W

1

20

1

AGC_FORCE on the CLC5902. Do not use.

Reserved

1b

R/W

0

20

2

AGC_RESET_EN on the CLC5902. Do not use.

AGC_HOLD_IC

1b

R/W

0

20

3

0=Normal closed-loop operation. 1=Hold integrator at initial condition. This affects both

channels.

AGC_LOOP_GAIN

2b

R/W

0

20

4:5:

Bit shift value for AGC loop. Valid range is from 0 to 3. This affects both channels.

Reserved

2B

R/W

0

21-22

7:0

AGC_COUNT on the CLC5902. Do not use.

AGC_IC_A

1B

R/W

0

23

7:0

AGC fixed gain for channel A. Format is an 8-bit, unsigned magnitude number. The channel

A DVGA gain will be set to the inverted three MSBs.