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AOUT

BOUT

82

78

G12

G10

SERIAL OUTPUT DATA, Active high

The 2’s complement serial output data is transmitted on these pins, MSB first. The

output bits change on the rising edge of SCK (falling edge if SCK_POL=1) and should

be captured on the falling edge of SCK (rising if SCK_POL=1). These pins are

tri-stated at power up and are enabled by the SOUT_EN control register bit. See Fig-

ure 10 and Figure 30 timing diagrams. In Debug Mode AOUT=DEBUG[1],

BOUT=DEBUG[0].

AGAIN[2:0],

BGAIN[2:0]

125:127

40:42

D4,A3,D5

J5,L4,M3

OUTPUT DATA TO DVGA, Active high

3 bit bus that sets the gain of the DVGA determined by the AGC circuit.

ASTROBE,

BSTROBE

124

43

C4

K5

DVGA STROBE, Active low

Strobes the data into the DVGA. See Figure 9 and Figure 35 timing diagrams.

SCK

80

H11

SERIAL DATA CLOCK, Active high or low

The serial data is clocked out of the chip by this clock. The active edge of the clock is

user programmable. This pin is tri-stated at power up and is enabled by the SOUT_EN

control register bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode out-

puts an appropriate clock for the debug data. If RATE=0 the input CK duty cycle will

be reflected to SCK.

SCK_IN

99

B11

SERIAL DATA CLOCK INPUT, Active high or low

Data bits from a serial daisy-chain slave are clocked into a serial daisy-chain master

on the falling edge of SCK_IN (rising if SCK_POL=1 on the slave). Tie low if not used.

SFS

81

F9

SERIAL FRAME STROBE, Active high or low

The serial word strobe. This strobe delineates the words within the serial output

streams. This strobe is a pulse at the beginning of each serial word (PACKED=0) or

each serial word I/Q pair (PACKED=1). The polarity of this signal is user programma-

ble. This pin is tri-stated at power up and is enabled by the SOUT_EN control register

bit. See Figure 10 and Figure 30 timing diagrams. In Debug Mode SFS=DEBUG[2].

POUT[15:0]

84,86:88,

90,91,

93:97,104:

106,

108,109

F12,F10,

E11,E12,

D11,D12,

E9,C12,D9,

C11,B12,

B9,A10,C8,

D7,C7

PARALLEL OUTPUT DATA, Active high

The output data is transmitted on these pins in parallel format. The POUT_SEL[2..0]

pins select one of eight 16-bit output words. The POUT_EN pin enables these out-

puts. POUT[15] is the MSB. In Debug Mode POUT[15..0]=DEBUG[19..4].

POUT_SEL[2:0]

112:114

D6,A7,B7

PARALLEL OUTPUT DATA SELECT, Active high

The 16-bit output word is selected with these 3 pins according to Table 2. Not used in

Debug Mode. For a serial daisy-chain master, POUT_SEL[2:0] become inputs from

POUT_EN

111

B8

PARALLEL OUTPUT ENABLE. Active low

This pin enables the chip to output the selected output word on the POUT[15:0] pins.

Not used in Debug Mode. Tie high if not used.

RDY

77

G9

READY FLAG, Active high or low

The chip asserts this signal to identify the beginning of an output sample period

(OSP). The polarity of this signal is user programmable. This signal is typically used

as an interrupt to a DSP chip, but can also be used as a start pulse to dedicated cir-

cuitry. This pin is active regardless of the state of SOUT_EN. In Debug Mode

RDY=DEBUG[3].

CKA,

CKB

20,

38

F2

K4

INPUT CLOCK. Active high

The clock inputs to the chip. The corresponding AIN and BIN signals are clocked into

the chip on the rising edge of this signal. CKA and CKB are OR’d together on chip to

create the CK signal. SI is clocked into the chip on the rising edge of CK. Tie low if not

used.

SI

46

J6

SYNC IN. Active low

The sync input to the chip. The decimation counters, dither, and NCO phase can be

synchronized by SI. This sync is clocked into the chip on the rising edge of CK (CK =

CKA + CKB). Tie this pin high if external sync is not required. All sample data is

flushed by SI. To properly initialize the DVGA ASTROBE and BSTROBE are asserted

during SI.

Signal

PQFP Pin

FBGA Pin

Description