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26

ure 38. The integrator saturates at these limits to prevent

overshoots as the integrator attempts to enter the valid

range. The AGAIN value is inver ted (EXP) and used to

adjust the gain of the incoming signal to provide a linear out-

put dynamic range. The relationship between the DVGA ana-

log gain (AGAIN) and the “FIXED TO FLOAT CONVERTER”

digital gain (EXP) is shown in Table 4. The DVGA’s compres-

sion of the incoming signal in the analog domain vs. the sub-

sequent expansion in the digital domain is shown in Figure

32.

The A G C m a y be f o r c ed t o f r ee r un b y se t t i n g

AG C_ H O L D _ I C lo w. W r itin g a n in itia l c o n d i t io n to

AGC_IC_A|B and then setting AGC_HOLD_IC high will force

the AGC to a fixed gain. The three MSBs of the value written

to AGC_IC_A|B are inverted and output to drive the DVGA.

Allowing the AGC to free run should be appropriate for most

applications. If the INH_EXP bit is not set, the DVGA gain

word (EXP) is routed to the “FLOAT TO FIXED CON-

VERTER” in the DDCs prior to the programmable decimation

filter. The EXP signals are delayed to account for the propa-

gation delay of the DVGA interface and the CLC5957 ADC.

0

10

20

30

40

50

60

-120

-100

-80

-60

-40

-20

0

20

0

5

10

15

20

25

30

-120

-100

-80

-60

-40

-20

0

20

ADDRESS

(a)

(b)

Figure 37. Example of programmed RAM contents

a. AGAIN sets the DVGA or analog gain value.

b. EXP sets the “FIXED TO FLOAT CONVERTER” or digital gain value.

c. 22-bit input to SHIFT-UP block in Figure 16 horizontally, linearized SHIFT-UP value vertically.

21

20

19

18

17

16

15

14

...

876543210

000 = -12dB

111 = +0dB

-12dB

14

13

12

11

10

987...

10LLLLLLL

001 = -6dB

110 = -6dB

-12dB

14

14

13

12

11

10

98...

210LLLLLL

010 = +0dB

101 = -12dB

-12dB

14

14

14

13

12

11

10

9

...

3210LLLLL

011 = +6dB

100 = -18dB

-12dB

14

14

14

14

13

12

11

10

...

43210LLLL

100 = +12dB

011 = -24dB

-12dB

14

14

14

14

14

13

12

11

...

543210LLL

101 = +18dB

010 = -30dB

-12dB

14

14

14

14

14

14

13

12

...

6543210LL

110 = +24dB

001 = -36dB

-12dB

14

14

14

14

14

14

14

13

...

76543210L

111 = +30dB

000 = -42dB

-12dB

14

14

14

14

14

14

14

14

...

876543210

d. The numbers in the center of the table represent the mixer output bits. ‘L’ represents a logic low.

0

Integrator Output

0

1

2

3

4

5

6

7

The min integrator

output must be

limited to 0 so that

the sign of AGAIN

is positive

For this range to be

the same size as all

others, the max

integrator output must

Figure 38. AGC integrator output limits