CLC5903 datasheet(13/29 Pages) NSC

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the compensation is dependent on timing and the accuracy

of the DVGA gain step. The CLC5903 allows the timing of the

gain compensation to be adjusted in the EXT_DELAY regis-

ter. This operating mode requires 21 bits (14-bit ADC output

+ 7-bit shift) to represent the full linear dynamic range of the

signal. The output word must be set to either 24-bit or 32-bit

to take advantage of the entire dynamic range available. The

CLC5903 can also be configured to output a floating point

format with up to 138dB of numerical resolution using only 12

output bits.

The “SHIFT UP” circuit will be discussed in the Four Stage

CIC filter section on page 14.

A 4-stage cascaded-integrator-comb (CIC) filter and a

two-stage decimate by 4 or 8 finite impulse response (FIR)

filter are used to lowpass filter and isolate the desired signal.

The CIC filter reduces the sample rate by a programmable

factor ranging from 8 to 2048 (decimation ratio). The CIC out-

puts are followed by a gain stage and then followed by a

two-stage decimate by 4 or 8 filter. The gain circuit allows the

user to boost the gain of weak signals by up to 42 dB in 6 dB

steps. It also rounds the signal to 21 bits and saturates at

plus or minus full scale.

The first stage of the two stage filter is a 21-tap, symmetric

decimate by 2 FIR filter (F1) with programmable 16 bit tap

weights. The coefficients of the first 11 taps are downloaded

to the chip as 16 bit words. Since the filter is a symmetric

configuration only the first 11 coefficients must be loaded.

The F1 section on page 15 provides a generic set of coeffi-

cients that compensate for the rolloff of the CIC filter and pro-

vide a passband flat to 0.01dB with 70 dB of out of band

rejection. A second coefficient set is provided that has a nar-

rower output passband and greater out-of-band rejection.

The second set of coefficients is ideal for systems such as

GSM where far-image rejection is more important than adja-

cent channel rejection.

The second stage is a 63 tap decimate by 2 or 4 programma-

ble FIR filter (F2) also with 16 bit tap weights. Filter coeffi-

cients for a flat response from -0.4FS to +0.4FS of the output

sample rate with 80dB of out of band rejection are provided

in the F2 section. A second set of F2 coefficients is also pro-

vided to enhance performance for GSM systems. The user

can also design and download their own final filter to custom-

ize the channel’s spectral response. Typical uses of program-

mable filter F2 include matched (root-raised cosine) filtering,

or filtering to generate oversampled outputs with greater out

of band rejection. The 63 tap symmetrical filter is down-

loaded into the chip as 32 words, 16 bits each. Saturation to

plus or minus full scale is performed at the output of F1 and

F2 to clip the signal rather than allow it to roll over.

The CLC5903 provides two sets of coefficient memory for

both F1 and F2. These coefficient memories can be indepen-

dently routed to channel A, channel B, or both channel A and

B with a crossbar switch. The coefficients can be switched on

the fly but some time will be required before valid output data

is available.

The Numerically Controlled Oscillator

The tuning frequency of each down converter is specified as

a 32 bit word (.02Hz resolution at CK=52MHz) and the phase

offset is specified as a 16 bit word (.005°). These two param-

eters are applied to the Numerically Controlled Oscillator

(NCO) circuit to generate sine and cosine signals used by

the digital mixer. The NCOs can be synchronized with NCOs

on other chips via the sync pin SI. This allows multiple down

converter outputs to be coherently combined, each with a

unique phase and amplitude.

The tuning frequency is set by loading the FREQ register

according to the formula FREQ = 232F/FCK, where F is the

desired tuning frequency and FCK is the chip’s clock rate.

FREQ is a 2’s complement word. The range for F is from

-FCK/2 to +FCK(1-2

-31)/2.

In some cases the sampling process causes the order of the

I and Q components to be reversed. Should this occur simply

invert the polarity of the tuning frequency F.

(a) Before Phase Dithering

(b) After Phase Dithering

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-160

-140

-120

-100

-80

-60

-40

-20

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-160

-140

-120

-100

-80

-60

-40

-20

Frequency Normalized to FS

Figure 17. Example of NCO spurs due to phase truncation

Complex NCO Output

Detailed Description (Continued)

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