CLC5903 datasheet(12/29 Pages) NSC

12 / 29 page

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Detailed Description

Control Interface

The CLC5903 is configured by writing control information

into 148 control registers within the chip. The contents of

these control registers and how to use them are described

under Control Register Addresses and Defaults on page 21.

The registers are written to or read from using the D[7:0],

A[7:0], CE, RD and WR pins (see Table for pin descrip-

tions). This interface is designed to allow the CLC5903 to

appear to an external processor as a memory mapped

peripheral. See Figure 15 for details.

The control interface is asynchronous with respect to the

system clock, CK (CK = CKA + CKB). This allows the regis-

ters to be written or read at any time. In some cases this

might cause an invalid operation since the interface is not

internally synchronized. In order to assure correct operation,

SI must be asserted after the control registers are written.

The D[7:0], A[7:0], WR, RD and CE pins should not be

driven above the positive supply voltage.

Master Reset

A master reset pin, MR, is provided to initialize the CLC5903

to a known condition and should be strobed after power up.

This signal will clear all sample data and all user pro-

grammed data (filter coefficients and AGC settings). All out-

puts will be disabled (tri-stated). ASTROBE and BSTROBE

will be asserted to initialize the DVGA values. Control Regis-

ter Addresses and Defaults on page 21 describes the control

Synchronizing Multiple CLC5903 Chips

A system containing two or more CLC5903 chips will need to

be synchronized if coherent operation is desired. To synchro-

nize multiple CLC5903 chips, connect all of the sync input

pins together so they can be driven by a common sync

strobe. Synchronization occurs on the rising edge of CKA|B

when SI goes back high. When SI is asserted all sample

data will be flushed immediately, the numerically controlled

oscillator (NCO) phase offset will be initialized, the NCO

dither generators will be reset, and the CIC decimation ratio

will be initialized. Only the configuration data loaded into the

microprocessor interface remains unaffected.

SI may be held low as long as desired after a minimum of 4

CK periods.

Input Source

The input crossbar switch allows either AIN, BIN, or a test

DDC. The AGC outputs, AG AIN and BG AIN , are not

switched. If AIN and BIN are exchanged the AGC loop will be

open and the AGCs will not function properly. AIN and BIN

should meet the timing requirements shown in Figure 7.

Selecting the test register as the input source allows the

AGC or DDC operation to be verified with a known input. See

the test and diagnostics section for further discussion.

Down Converters

A detailed block diagram of each DDC channel is shown in

Figure 16. Each down converter uses a complex NCO and

mixer to quadrature downconvert a signal to baseband. The

“FLOAT TO FIXED CONVERTER” treats the 15-bit mixer out-

put as a mantissa and the AGC output, EXP, as a 3-bit expo-

nent. It performs a bit shift on the data based on the value of

EXP. This bit shifting is used to expand the compressed

dynamic range resulting from the DVGA operation. The

DVGA gain is adjusted in 6dB steps which are equivalent to

each digital bit shift.

Digitally compensating for the DVGA gain steps in the

CLC5903 causes the DDC output to be linear with respect to

the DVGA input. The AGC operation will be completely trans-

parent at the CLC5903 output.

The exponent (EXP) can be forced to its maximum value by

setting the EXP_INH bit. If

is the DDC input, the sig-

nal after the “FLOAT TO FIXED CONVERTER” is

(1)

for the I component. Changing the ‘cos’ to ‘sin’ in this equa-

tion will provide the Q component.

The “FLOAT TO FIXED CONVERTER” circuit expands the

dynamic range compression performed by the DVGA. Sig-

nals from this point onward extend across the full dynamic

range of the signals applied to the DVGA input. This allows

the AGC to operate continuously through a burst without pro-

ducing artifacts in the signal due to the settling response of

the decimation filters after a 6dB DVGA gain adjustment. For

example, if the DVGA input signal were to increase causing

the ADC output level to cross the AGC threshold level, the

gain of the DVGA would change by -6dB. The 6dB step is

allowed to propagate through the ADC and mixers and is

compensated out just before the filtering. The accuracy of

NCO

FREQ_A

PHASE_A

Data @ FCK

EXPONENT

EXP

OUTPUT

CIRCUIT

Figure 16. CLC5903 Down Converter, Channel A (Channel B is identical)

SIN

COS

(from AGC)

x3 n

()

xin n

()

MUXA

= FS (FSAMPLE)

Data @ FCK/N

Data @ FCK/N*2

Data @ FCK/N*2*F2_DEC

= OFS (Output FSAMPLE)

N = DEC + 1

in n

()

3 n

() x

in n

()

ωn

()

cos

•

EXP

•

Detailed Description (Continued)

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