PC87365 datasheet(170/215 Pages) NSC

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10.0 Temperature Sensor (TMS) (Continued)

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10.2.1

Two register banks control TMS operation. The first part of each bank is a set of registers common to all banks. The second

part of each bank contains registers which are specific to that bank. All registers use the same 16-byte address space to

indicate offsets 00h through 0Fh. The software selects the currently active bank using the Bank Select register (TMSBS) —

see Figure 34. Bank 0 is selected after reset.

Figure 34. Register Bank Architecture

10.2.2

TOS, THIGH and TLOW Limits, OTS and ALERT Output, IRQ and SMI

The temperature reading is compared to three limits: TOS,THIGH and TLOW. If the temperature reading is outside any of

these limits, the respective status bit (Channel Overtemperature Limit Exceeded, Channel Temp High Limit Exceeded or

Channel Temp Low Limit Exceeded) in the TCHCFST register is set. The status bit stays active until it is cleared by the soft-

ware. An ALERT status bit in the TEVSTS register is set when the Channel Temp High Limit Exceeded or Channel Temp

Low Limit Exceeded bit for the respective channel is set. The channel’s Overtemperature Event status in the TEVSTS reg-

ister is set when the Channel Overtemperature Limit Exceeded bit is set.

The OTS output is used to indicate to the system that the overtemperature limit has been exceeded. The OTS Output Enable

bit in the TCHCFST register enables the OTS output to be active when the OTS status of the channel is active. In addition

to the combined OTS output, there is a separate output for the remote 1 (OTS1) and remote 2 (OTS2) channels.

The ALERT output is used to indicate to the system that the current temperature is outside the high/low limits. The ALERT

output Enable bit in the TCHCFST register enables the ALERT output to be active when the Channel Temp High Limit Ex-

ceeded or the Channel Temp Low Limit Exceeded status bit in TCHCFST register is set.

The SMI output generates an interrupt if any enabled SMI event occurs. Each bit in the TEVSTS register has a correspond-

ing SMI Enable bit in the TEVSMI register. When any status bit and its corresponding SMI Enable bit are set, the SMI output

is active.

The IRQ output generates an interrupt if any enabled IRQ event occurs. Each bit in the TEVSTS register has a correspond-

ing IRQ Enable bit in the TEVIRQ register. When any status bit and its corresponding IRQ Enable bit are set, the IRQ output

is active.

Offset 0Eh

TMSBS (09h)

Common

Registers

All Banks

Offset 0Ah

BANK 1

BANK 0

Offset 08h

Offset 00h

for

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