PC87365 datasheet(167/215 Pages) NSC

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9.0 Voltage Level Monitor (VLM) (Continued)

167

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9.7

USAGE HINTS

9.7.1

Calculating the Channel Delay

The channel delay is the interval between the time a new channel is selected and the time the channel voltage can be mea-

sured. The reason for this delay is to allow the voltage to charge all internal capacitors to guarantee accuracy of the mea-

surement. This delay period depends on characteristics of the input (resistance and capacitance) and of the external circuit.

Figure 31 shows the schematic of the input and its equivalent R-C circuit. The sampling time should be long enough to guar-

antee that the voltage settles on the capacitor CS. The voltage on CS should be stable before the measurement starts. The

RAIN and CAIN values represent the input path serial resistance and parallel capacitance. RAIN is the serial resistance of the

multiplexer, Sample & Hold switch and other parasitic resistors. CAIN is the parallel capacitance of the input pin, pad, lead-

frame, CS, etc. The required sampling time is determined by RAIN and CAIN together with the input source resistance

RSOURCE and parasitic capacitance CP. Table 50 can be used as a reference for calculating the sample time. Channel Delay

of the VCNVR register should be programmed accordingly.

0Ch

(Bank

0-10)

CHVH

Channel Voltage High Limit Value

0Dh

(Bank

0-10)

CHVL

Channel Voltage Low Limit Value

0Eh-

0Fh

Reserved

Table 50. Delay Setting Example

External

Elements

Delay Time

(ns)

RSOURCE

Ω]

[pF]

0.1

110

900

3200

Bits

RAIN

CAIN

Input

Signal

RSOURCE

Figure 31. Analog Input Schematic Diagram and Equivalent R-C Circuit

Analog

AD0

AD1

AD2

AD3

AD4

AD5

AD6

MUX

VIN

RSOURCE

VIN

CP is the parasitic capacitor including the external

RAIN is the equivalent serial resistance of all serial

elements inside the chip (pin, bonding, MUX, Sample &

elements (PCB capacitance etc.).

Hold switch, layout).

CS is the sampling capacitor.

CAIN is the equivalent parallel capacitance of the chip

parasitic capacitances and the CS capacitor.

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